JPS59107520A - Semiconductor substrate - Google Patents

Semiconductor substrate

Info

Publication number
JPS59107520A
JPS59107520A JP21695982A JP21695982A JPS59107520A JP S59107520 A JPS59107520 A JP S59107520A JP 21695982 A JP21695982 A JP 21695982A JP 21695982 A JP21695982 A JP 21695982A JP S59107520 A JPS59107520 A JP S59107520A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
mirror
face
finished
cleavage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21695982A
Other languages
Japanese (ja)
Inventor
Shigeyuki Iiyama
重幸 飯山
Junji Watanabe
純二 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP21695982A priority Critical patent/JPS59107520A/en
Publication of JPS59107520A publication Critical patent/JPS59107520A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To reduce the generation of breaking on the titled semiconductor substrate by a method wherein the side face thereof is formed into mirror face. CONSTITUTION:A surface 1 is finished in mirror face having no distortion and the side face of the semiconductor substrate, having the back side 4 as cut-off face and the side face 2 of 1.5mumRmax of polished finish, is finished in the mirror face of 0.2mumRmax or below in surface roughness by performing chemical polishing. When said side face is finished in mirror face, the side face is formed into the state wherein defects such as notches, an uneven surface, cracks, scratches and the like, where stress concentration is generated and will be the starting point of a cleavage causing breakages, are almost removed. As a result, the generation of a cleavage can be prevented, thereby enabling to increase the breakage strength of the semiconductor substrate.

Description

【発明の詳細な説明】 本発明は半導体装置を製造するのに用いられる半導体基
板に関し、特に製造工廊中に生ずる破Jj4を防止する
ようにした半導体基板に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor substrate used for manufacturing semiconductor devices, and more particularly to a semiconductor substrate designed to prevent damage Jj4 from occurring during a manufacturing process.

集積回路のような半導体装置を製造するために用いらi
する半導体基板は第1図に示すような略々円板状のウェ
ハのものが用いられている。図において、/は無歪の鏡
面に研磨仕上げされた主面で、表面又はミラー面と呼ば
flている。コはウェハの外周縁に沿った円筒面で、通
常は単結晶棒を輪切Y)Kする前に粗い砥石で研削仕上
げしである。3は半導体基板の外周縁の一部に設けられ
たオリエンテーションフラットと呼ばれる〔/lo〕方
向に平行な面で、通常は単結晶棒を輪切りにする前に粗
い砥石で成形研削仕上げしである。そして、主面lの反
対側の面は通常切断砥石で切断されたままの面で、裏面
と呼ばれる面でなっている。ここf 円筒面、2及びオ
リエンテーションフラット3hその数例を第2図に断面
形状の模式図で示すように種々の形状の面取り成形面で
なっている。なお、第2 @ ij: FA /図のA
−A’面での断面を示している。
Used to manufacture semiconductor devices such as integrated circuits
The semiconductor substrate used is a substantially disk-shaped wafer as shown in FIG. In the figure, / is a main surface polished to a distortion-free mirror surface, which is called a surface or mirror surface. This is a cylindrical surface along the outer periphery of the wafer, which is usually ground with a coarse grindstone before cutting the single crystal bar into rings. 3 is a plane parallel to the [/lo] direction called an orientation flat provided on a part of the outer periphery of the semiconductor substrate, and is usually finished by forming and grinding with a coarse grindstone before slicing the single crystal rod into rounds. The surface opposite to the main surface l is the surface that has been cut by the cutting wheel and is called the back surface. The cylindrical surface 2 and the orientation flat 3h are chamfered surfaces of various shapes, some examples of which are shown in the schematic cross-sectional view of FIG. In addition, the second @ ij: FA /A in the figure
-A cross section taken along the A' plane is shown.

第2図(イ)は上下テーパ面取り、(ロ)図は半円面取
り、(ハ)、に)図は半楕円面取11)、G]+図は放
物線面取り、(へ)図は上下几面取りである。
Figure 2 (a) shows upper and lower taper chamfering, (b) shows semicircular chamfering, (c), 2) shows semi-elliptical chamfer11), G]+ shows parabolic chamfering, and (f) shows upper and lower chamfering. It is chamfered.

上記集積回路のような半導体装置を製造するのに用いら
れる半導体基板の材料としては従来より8iでなるもの
が用いられ−Cいたが、最近は0aAsのようにm−V
族半導体でなるものも用いるようになってきた。
Conventionally, materials made of 8i-C have been used as materials for semiconductor substrates used to manufacture semiconductor devices such as the above-mentioned integrated circuits, but recently m-V materials such as 0aAs have been used.
Devices made of group semiconductors have also come to be used.

これらの半導体はいずれも結晶構造がダイヤモンドない
しは閃亜鉛鉱型の構造であるために、へき開面を有して
いる。へき開面は割るだけで非常に均一性の良い平坦面
が得られるので、半導体レーザの反射面として活用され
る等の利点ともなるが、逆に製造工程中に半導体基板が
割11フζす、かけたりする原因となる欠点ともなって
いた。
All of these semiconductors have a diamond or zincblende crystal structure and therefore have cleavage planes. A cleavage plane can be used to obtain a flat surface with very good uniformity simply by breaking it, so it has the advantage of being used as a reflection surface for semiconductor lasers. It was also a drawback that caused problems.

特に(iaAs等の薯−V族半導体はSiよりもへき開
性が強いので、製造工程中の半導体基板の破損が問題と
なる。′πλ図に示した種々の面取りは上記製造工程中
の半導体基板の割れ等を防止することも目的としてなさ
れているものであるが、fへ然として、破損は発生して
おり、%(C0aAs基)反においては破損する確率が
高く、半導体装置の歩留りを低下させる欠点となってい
た。
In particular, since (A-V group semiconductors such as iaAs have a stronger cleavage property than Si, damage to the semiconductor substrate during the manufacturing process becomes a problem.) The various chamfers shown in the 'πλ diagrams Although this is intended to prevent cracking, etc., damage has naturally occurred to This was a drawback.

本発明は半導体基板の破損の原因が外周部における研削
に基づく欠陥(凹凸、切欠き、クラック。
In the present invention, the cause of damage to a semiconductor substrate is defects (irregularities, notches, cracks) caused by grinding on the outer periphery.

引っかききす等)の存在にあると考え、この欠陥を除去
するために、半導体基板の側面を鏡面にした破損の少な
い半導体基板を提案するものである。
This is due to the presence of scratches, etc.), and in order to eliminate these defects, we propose a semiconductor substrate with mirror-finished sides so that it is less likely to be damaged.

すなわち、本発明の寿施例は例えば第2図に示した種々
の面取り成形面でなる円筒面を鏡面にしたものである。
That is, in the longevity embodiment of the present invention, for example, the cylindrical surface made of various chamfered surfaces shown in FIG. 2 is made into a mirror surface.

第3図は本発明の詳細な説明するために用いた種々の試
料の断面模式図で、(a)図は表面/が無歪の鏡面仕上
げ、裏面qが切断面、 (fil]面2が約/jμm1
″tmaxの研削仕上げのイ)ので、(h)図は(a)
図に示したものに比べて裏面が化学エッチ仕上けOてな
っている点が違っているだけで、他の面は(a)図のも
のと同じであり、(c)図は(hJ図に示したものの側
面を化学エツチングによって表面あらさをO1jμmR
,lax程度に仕上げたものであり、(d)図は(a)
図に示したものの側面をり一ミカルボリヅングにより表
面あらさ02μm”In;IX以下の鏡面に仕上げたも
のであり、(c)図は(d)図に示したものの裏面’r
 fに学エッチ仕上げにしたものであり、(f)図は(
d)図に示したものの裏面を無歪の鏡面(表面と同じ程
度に)に仕上げたものである。
Fig. 3 is a schematic cross-sectional view of various samples used to explain the present invention in detail, in which (a) the front surface has a mirror finish with no distortion, the back surface q has a cut surface, and the (fil] surface 2 has a mirror finish without distortion. Approximately/jμm1
″tmax grinding finish a), so (h) figure is (a)
Compared to the one shown in the figure, the only difference is that the back side has a chemically etched finish. The surface roughness was reduced to O1jμmR by chemical etching the side surface of the one shown in
, lax, and (d) is similar to (a).
The side surface of the object shown in the figure is polished to a mirror surface with a surface roughness of 02μm or less by mirror boring, and (c) is the back surface of the object shown in (d).
(f) has an etch finish, and (f) is (
d) The back side of the one shown in the figure is finished to a distortion-free mirror surface (same level as the front side).

こil、らの試料はいずれも〔//θ〕方向に平行な側
面を持ち、幅j〜!q]、長さ30〜≠0朋、厚さ30
0〜l/−00μmの短冊片からなり、側面は半楕円面
取り形状となっている。
Both of these samples have side surfaces parallel to the [//θ] direction and have a width j~! q], length 30~≠0, thickness 30
It consists of a strip of 0 to 1/-00 μm, and the side surface has a semi-elliptical chamfered shape.

ここで(a)図に示すものは現在0aAs ウニ・・で
通常用いられている表面仕上げ状態に一致させたもので
あり、(C)図に示すものは現在ンリコンウェハで通常
用いらflている表面仕上げ状t’14 (i(一致さ
せたものである。結晶月料としては、破Jυが生じやす
い0aAs基板で第3図(a)〜(r)に示すぞ、lt
ぞれの形状のものを、参考データを得るために8+基板
で第3図(b)、 (c)に九す形状のものを用いた。
Here, the surface finish shown in (a) corresponds to the surface finish currently commonly used in 0aAs sea urchins, and the one shown in (C) corresponds to the surface finish currently commonly used in silicon wafers. The finished state t'14 (i) is made to match.The crystal material used is a 0aAs substrate that is prone to breakage, as shown in Figures 3(a) to (r).lt
For each shape, in order to obtain reference data, a nine-square shape was used on an 8+ board as shown in FIGS. 3(b) and 3(c).

本発明者らは上記試料を用いで、両端自由支持で、中央
部に集中荷重を加える曲は破壊実験を行い、種々の形状
のものの曲げ破壊応力を比較してみた。
The present inventors conducted a bending fracture experiment using the above sample, with both ends freely supported and a concentrated load applied to the center, and compared the bending fracture stresses of various shapes.

第j図は第3図に示し/こ種々の表面形状の試料の曲げ
破壊応力の値を示したものであり、そJlぞilの試料
のいすノ1の面が圧縮応力を受け、いずれの面が引張り
応力を受けたかを示しである。図より、側面を鏡面に仕
上げた試料は側面が研削仕上げの試料や表面あらさ0.
3 ltmTLmax程度の化学エッチ仕上げの試料に
比べると井恰≠破壊応力が大幅に改善されている。本発
明のCi a A s基板は現在使われている基板の約
3倍の強度と々っており略々現在使わil、ている81
基&程度の値となっており、本発明のSt基板は現在使
わilている基板の約1倍の強度になっている。
Figure J shows the bending fracture stress values of samples with various surface shapes shown in Figure 3. This indicates whether the surface is under tensile stress. From the figure, we can see that samples with mirror-finished sides, samples with ground-finished sides, and samples with surface roughness of 0.
Compared to a sample with a chemically etched finish of about 3ltmTLmax, the fracture stress is significantly improved. The Cia As substrate of the present invention has approximately three times the strength of the currently used substrates, and is approximately as strong as the currently used substrates81.
The strength of the St substrate of the present invention is about 1 times that of the currently used substrates.

第グ図に示したように、側面をo、2/im顯。28以
下程度((鏡面仕上げした試料の破壊強度が向上するの
は以下の理由によると考えらilる。
As shown in the figure, the sides are o, 2/im. 28 or less ((It is thought that the reason why the fracture strength of mirror-finished samples is improved is as follows.

側面を鏡面に仕−Fげると破損の原因であるへき開の開
始点となる応力集中の生ずる切り欠き、凹凸・ クラッ
ク、引っかききす等の欠陥がほとんど除去された状B&
てなる。こilによってへき開の発生が防げるために破
壊強度が増大するという考えである。この考えを裏イリ
ける点として、F記に示す実験結果がある。
When the sides are polished to a mirror finish, most of the defects such as notches, unevenness, cracks, and scratches that cause stress concentration and become starting points for cleavage that cause damage have been removed.
It becomes. The idea is that the fracture strength increases because the coil prevents the occurrence of cleavage. The experimental results shown in Section F contradict this idea.

側面を鏡面仕上げにしていない試料1d材料カ学的に計
算した最大応力が加わると、へき開開始箇所よりへき開
?、すれが生じて破損するが、fl11面を鏡面仕上げ
にした試料ifI料カ学的に計3′Iさ1する最大応力
が加わっても々がなかへき開割れが発生せず、それ以上
の応力が加わって破壊するときには多数の破片となる場
合が多かった。多数の破片として破損することは応力が
ウェハ内で弾性エネルギとして蓄積さitでいるためで
あり、上記考えを裏付けている。
When a mechanically calculated maximum stress is applied to sample 1d material whose side surfaces are not mirror-finished, cleavage occurs from the cleavage starting point? However, even if the maximum stress of 3'I1 is applied to the sample ifI, whose fl11 surface is mirror-finished, no cleavage cracks occur, and no further stress occurs. When it was destroyed by the addition of water, it often broke into many pieces. The reason why the wafer breaks into multiple pieces is because the stress is stored as elastic energy within the wafer, supporting the above idea.

更に、第≠図において、Q、 j /+m前後の凹凸が
flll1面に存在するもの(化学エツチングで仕上げ
た第3図(c)の試料)においては破壊強度が僅かしか
改善さJlていない点より、0..3− 、am程度の
表面の凹凸はへき開の開始点(でなっていることを示し
ている。こ)1よりへき開の開始点をなくすために1−
i表面の凹凸がQ2.am程度より少ないことが必要と
なることになる。
Furthermore, in Figure ≠, the fracture strength is only slightly improved in the case where unevenness around Q, j /+m exists on the full surface (the sample in Figure 3 (c) finished by chemical etching). From 0. .. 3-, the irregularities on the surface of the order of am indicate the starting point of cleavage.
i The unevenness of the surface is Q2. It will be necessary to have less than about am.

以りの実験において、第3図((1)〜(f)に示した
試料はポリッシングで側面を鏡面仕上げにした場合で説
明したが、本発明が目的とする破壊強度の大きな半導体
基板は110面に応力集中の発生ずる欠陥を除去するこ
とによって得られるのであるから、鏡面仕上げにする手
法はポリッシングだけでなく、エツチング等いずれの手
法によっても良いことは明らかであろうし、捷だ、面取
りの形状には何ら関係のないことも明らかであろう。更
に、半導体基板の材料も()aAsと81の場合を示し
たが他の半導体基板でも良いことは明らかであろう。
In the experiment described above, the samples shown in FIG. 3 ((1) to (f) were polished to a mirror finish on the sides, but the semiconductor substrate with high breaking strength, which is the objective of the present invention, Since it can be obtained by removing defects that cause stress concentration on the surface, it is obvious that a mirror finish can be achieved not only by polishing but also by etching or other methods. It is clear that there is no relation to the shape.Furthermore, although the material of the semiconductor substrate is (aAs) and 81 is shown, it is clear that other semiconductor substrates may be used.

、以上の説明で半導体基板の側面が02μm程度以下の
表面凹凸のものであれば破壊強度の大きなもの、すなわ
ち、破損の発生確率が小さなものが得らねることが明ら
かとなったが、表面の凹凸が0、2μm程度以下の半導
体はその面が鏡面になっている。
From the above explanation, it has become clear that if the side surface of the semiconductor substrate has surface irregularities of approximately 0.2 μm or less, it will not be possible to obtain a product with high fracture strength, that is, a product with a small probability of occurrence of damage. A semiconductor whose unevenness is about 0.2 μm or less has a mirror surface.

これより、ウェハの外周側面が鏡面になっている半導体
基板が破損の発生確率の小さな半導体基板であることに
なる。
From this, it follows that a semiconductor substrate whose outer peripheral side surface of the wafer has a mirror surface is a semiconductor substrate with a low probability of occurrence of damage.

半導体装置は年々高密度化、15速化が図ら相ているが
、これに伴なって製造工程も複”、(flてなって来て
いる。このため、半導体基板を処理十ろ工程も年々増加
しており、半導体基板が破擬する確率が高くなっている
Semiconductor devices are becoming more dense and faster each year, and along with this, the manufacturing process is also becoming more complex.As a result, the processing steps for semiconductor substrates are also becoming more complex. The probability of semiconductor substrate failure is increasing.

寸だ、最近は半導体装置製造の自動化が3イ(められて
いるが、この自動化工程は連続的に処工[1てilてい
るので、工程中に半導体基板の64(損が生ずること(
d全工程を停止することにもなり、半導体基板の破]l
は増々大きな問題となって来ている。
Recently, automation of semiconductor device manufacturing has been promoted, but since this automated process involves continuous processing, there is a risk of damage to semiconductor substrates during the process.
d It will also stop the entire process and damage the semiconductor substrate]l
is becoming an increasingly big problem.

本発明は上記問題を解決するものであるから、半導体製
造に大幅な改善を与えることになる。
Since the present invention solves the above problems, it provides a significant improvement in semiconductor manufacturing.

また、半導体基板は破損を防ぐためにつ=’・の径が犬
きくなるほど、厚さも厚くシ〔来た。しかし、本発明の
半導体基板を用いt’tば、従来のものよりも厚さを薄
くすることがoJ能となる。半^j体基板の厚さを薄く
することは、lインゴットから多くの半導体基板が得ら
fすることによる経済化の利点があるが、半導体基板の
自重が破損の要因となっている点があるため、この点よ
り、破損の低減化にも寄Jiすること[なり、従来のウ
−17・径と厚さの関係を改善できる可能性も有するこ
とになる。
Also, to prevent damage to semiconductor substrates, the larger the diameter of the semiconductor substrate, the thicker it becomes. However, if the semiconductor substrate of the present invention is used, it becomes possible to make the thickness thinner than that of the conventional one. Reducing the thickness of the semi-conductor substrate has the advantage of making it more economical because more semiconductor substrates can be obtained from the ingot, but the problem is that the weight of the semiconductor substrate becomes a factor in damage. Therefore, from this point of view, it also contributes to the reduction of breakage, and there is also the possibility of improving the relationship between the diameter and thickness of the conventional U-17.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は半導体基板を示す斜視図、第2図は数例の面取
り成形面を示す断面模式図、第3図は本発明の効果を示
すために用いた種々の試料の断面模式図、第≠Mは破壊
応力を示す図である。 l・・主面、λ・・・円筒面、3−オリエンテーショ/
フラット、<L・・・裏面。 尋 1 副
FIG. 1 is a perspective view showing a semiconductor substrate, FIG. 2 is a schematic cross-sectional view showing several examples of chamfered molding surfaces, FIG. 3 is a schematic cross-sectional view of various samples used to demonstrate the effects of the present invention, and FIG. ≠M is a diagram showing fracture stress. l...principal surface, λ...cylindrical surface, 3-orientation/
Flat, <L...Back side. fathom 1 vice

Claims (1)

【特許請求の範囲】[Claims] ウェハの外周側面が鏡面になっていることを特徴とする
半導体基板。
A semiconductor substrate characterized by having a mirror surface on the outer peripheral side of the wafer.
JP21695982A 1982-12-13 1982-12-13 Semiconductor substrate Pending JPS59107520A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21695982A JPS59107520A (en) 1982-12-13 1982-12-13 Semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21695982A JPS59107520A (en) 1982-12-13 1982-12-13 Semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS59107520A true JPS59107520A (en) 1984-06-21

Family

ID=16696593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21695982A Pending JPS59107520A (en) 1982-12-13 1982-12-13 Semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS59107520A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61159740A (en) * 1984-10-25 1986-07-19 タンデム コンピユ−タ−ズ インコ−ポレ−テツド Miniaturization of wafer
JPS62263626A (en) * 1986-05-09 1987-11-16 Mitsubishi Metal Corp Semiconductor wafer
JPH02100319A (en) * 1988-10-07 1990-04-12 Fujitsu Ltd Manufacture of semiconductor device
JPH03280537A (en) * 1990-03-29 1991-12-11 Shin Etsu Handotai Co Ltd Epitaxial growth substrate
JPH0496247A (en) * 1990-08-03 1992-03-27 Shin Etsu Handotai Co Ltd Measurement of semiconductor wafer and particles thereof

Citations (2)

* Cited by examiner, † Cited by third party
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JPS55121643A (en) * 1979-03-13 1980-09-18 Toshiba Corp Fabricating method of semiconductor element
JPS5958827A (en) * 1982-09-28 1984-04-04 Toshiba Corp Semiconductor wafer and method and apparatus for manufacturing semiconductor wafer

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55121643A (en) * 1979-03-13 1980-09-18 Toshiba Corp Fabricating method of semiconductor element
JPS5958827A (en) * 1982-09-28 1984-04-04 Toshiba Corp Semiconductor wafer and method and apparatus for manufacturing semiconductor wafer

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61159740A (en) * 1984-10-25 1986-07-19 タンデム コンピユ−タ−ズ インコ−ポレ−テツド Miniaturization of wafer
JPS62263626A (en) * 1986-05-09 1987-11-16 Mitsubishi Metal Corp Semiconductor wafer
JPH079873B2 (en) * 1986-05-09 1995-02-01 三菱マテリアル株式会社 Semiconductor wafer
JPH02100319A (en) * 1988-10-07 1990-04-12 Fujitsu Ltd Manufacture of semiconductor device
JPH03280537A (en) * 1990-03-29 1991-12-11 Shin Etsu Handotai Co Ltd Epitaxial growth substrate
JPH0496247A (en) * 1990-08-03 1992-03-27 Shin Etsu Handotai Co Ltd Measurement of semiconductor wafer and particles thereof

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