JPH079873B2 - Semiconductor wafer - Google Patents
Semiconductor waferInfo
- Publication number
- JPH079873B2 JPH079873B2 JP61106293A JP10629386A JPH079873B2 JP H079873 B2 JPH079873 B2 JP H079873B2 JP 61106293 A JP61106293 A JP 61106293A JP 10629386 A JP10629386 A JP 10629386A JP H079873 B2 JPH079873 B2 JP H079873B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- curved surface
- curvature
- radius
- inclined surfaces
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Mechanical Treatment Of Semiconductor (AREA)
Description
【発明の詳細な説明】 「産業上の利用分野」 本発明は、半導体ウエハに係わり、特に、周縁部に面取
りが施された半導体ウエハに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer, and more particularly to a semiconductor wafer having a peripheral edge chamfered.
「従来の技術」 一般に、トランジスタやICの製造に用いられる半導体ウ
エハにあっては、搬送時や移載時における他の部材との
衝突等によって欠けが発生することがあり、これを防止
するために、最も欠けが発生しやすい部分である周縁部
に、面取りを施すことが実施されている。“Prior art” Generally, in semiconductor wafers used for manufacturing transistors and ICs, chipping may occur due to collision with other members during transportation or transfer, and in order to prevent this In addition, chamfering is performed on the peripheral edge portion where the chipping is most likely to occur.
そして、このような面取り形状の具体例として、従来に
おいては、特開昭53−10966号公報や特開昭58−100432
号公報で既に提案されている。As a concrete example of such a chamfered shape, conventionally, JP-A-53-10966 and JP-A-58-100432 are known.
It has already been proposed in the Gazette.
前者は、第２図に示すように、半導体ウエハＳの表裏面
の周縁角部を全周に亙って切削することにより、一定の
曲率を有する湾曲面１・２を形成し、該湾曲面１・２と
外周端面３とによって面取り面を形成したもので、該湾
曲面１・２の大きさは、該湾曲面１・２と半導体ウエハ
Ｓの表裏面との接点から前記外周端面３に至る距離Ａ
と、該外周端面３の半導体ウエハＳの厚さ方向における
距離Ｂを、以下の如く設定することにより規制したもの
である。As shown in FIG. 2, the former forms curved surfaces 1 and 2 having a constant curvature by cutting the peripheral corners of the front and back surfaces of the semiconductor wafer S over the entire circumference. A chamfered surface is formed by the outer peripheral end surface 3 and the outer peripheral end surface 3, and the size of the curved surface 1 and 2 is from the contact point between the curved surface 1.2 and the front and back surfaces of the semiconductor wafer S to the outer peripheral end surface 3. Distance A
The distance B of the outer peripheral end face 3 in the thickness direction of the semiconductor wafer S is regulated by setting as follows.
Ａ≧0.2mm Ｂ＝0.15mm〜（Ｗ−0.08）mm 但し、Ｗは半導体ウエハＳの厚みを示す。A ≧ 0.2 mm B = 0.15 mm to (W−0.08) mm where W represents the thickness of the semiconductor wafer S.
また、後者は、第３図に示すように、半導体ウエハＳの
周縁部を楕円に近い湾曲面４とすることにより、面取り
面を形成したもので、厚みＷを短径とするとともに、前
記湾曲面４と半導体ウエハＳの表裏面との接点から半導
体ウエハＳの外周端との距離Ｃを設定して長径とし、こ
れによって楕円形状を設定することにより、前記湾曲面
４すなわち面取り面の形状を規制したものである。In the latter case, as shown in FIG. 3, a chamfered surface is formed by forming the peripheral portion of the semiconductor wafer S into a curved surface 4 close to an ellipse. By setting the distance C from the contact point between the surface 4 and the front and back surfaces of the semiconductor wafer S to the outer peripheral edge of the semiconductor wafer S to obtain the major axis, and thereby setting the elliptical shape, the shape of the curved surface 4, that is, the chamfered surface It is regulated.
「発明が解決しようとする問題点」 本発明は、前述した従来の技術における次のような問題
点を解決せんとするものである。"Problems to be Solved by the Invention" The present invention is intended to solve the following problems in the above-described conventional techniques.
すなわち、前述したように面取りが施されたいずれの半
導体ウエハＳにおいても、その表裏面とほぼ直交する方
向に沿った外力に対しては、その面取りの作用により、
周縁部における欠け等の発生を抑制することができる
が、前記表裏面に沿う方向の外力に対しては、前述した
面取りによる欠け防止作用が低下してしまうといった問
題点がある。That is, in any of the semiconductor wafers S that have been chamfered as described above, the chamfering action causes an external force along a direction substantially orthogonal to the front and back surfaces thereof to
Although it is possible to suppress the occurrence of chipping or the like at the peripheral portion, there is a problem that the chipping prevention effect due to the chamfering described above is deteriorated with respect to external force in the direction along the front and back surfaces.
このような問題点は、半導体ウエハＳを表裏面方向に沿
って搬送するとともに、半導体ウエハＳの周端面を搬送
方向と直交する面に当接させることによって該半導体ウ
エハＳの停止や位置決めを行なう試験を実施した際に知
見したものである。Such a problem is that the semiconductor wafer S is transported along the front and back directions, and the peripheral end surface of the semiconductor wafer S is brought into contact with a surface orthogonal to the transport direction to stop or position the semiconductor wafer S. It was discovered when the test was conducted.
その発生原因として、前者においては、湾曲面１・２と
外周端面３との連続部に角部が形成されているととも
に、該角部に半導体ウエハＳの停止時の外力が大きく加
わってしまうこと、また、後者においては、面取り部の
曲率が小さく、これによって、前述した外力が加わった
場合に、面取り部に集中荷重が発生してしまうこと等が
考えられる。As a cause of the occurrence, in the former case, a corner is formed in a continuous portion between the curved surfaces 1 and 2 and the outer peripheral end surface 3, and an external force when the semiconductor wafer S is stopped is greatly applied to the corner. Further, in the latter case, the curvature of the chamfered portion is small, which may cause a concentrated load on the chamfered portion when the above-mentioned external force is applied.
そして、半導体ウエハＳの素子化工程の自動化や超LSI
化に伴う製造装置の複雑化により、前述したような半導
体ウエハＳの搬送および停止方法を採用する箇所が増加
する傾向にあり、これによって欠けの発生する確率が高
められるとともに、該欠けによって発生させられる微少
欠片が、半導体ウエハＳへの表面に付着してその機能を
阻害し、トランジスタやICの歩留りを低下させてしまう
ことが想定されることから、その対策が要望されてい
る。Then, automation of the process of converting the semiconductor wafer S into elements and VLSI
Due to the increase in complexity of the manufacturing apparatus, there is a tendency that the number of places where the method of transporting and stopping the semiconductor wafer S as described above is adopted increases, which increases the probability of occurrence of chipping and causes the chipping to occur. Since it is assumed that the minute fragments that are formed adhere to the surface of the semiconductor wafer S and impede its function, thereby lowering the yield of transistors and ICs, a countermeasure is required.
「問題点を解決するための手段」 本発明は、前述した従来の技術における問題点を有効に
解消し得る半導体ウエハを提供せんとするもので、該半
導体ウエハは、特に、周縁部に面取りが施された半導体
ウエハであって、前記面取りの形状が、半導体ウエハの
表裏面に、半径方向外方にいくにしたがい漸次厚さ方向
内方へ向かうように形成された一対の傾斜面と、これら
の各傾斜面の外方端部間を連絡する湾曲面とによって形
成され、かつ、該湾曲面が、前記厚さ方向中心部から半
導体ウエハの表裏面に向かって延びる第１の湾曲面と、
該第１の湾曲面を前記各傾斜面へ滑らかに連絡する第２
の湾曲面とを備え、前記第１の湾曲面の曲率半径が第２
の湾曲面の曲率半径よりも大きく形成されていることを
特徴とする。"Means for Solving Problems" The present invention is to provide a semiconductor wafer capable of effectively solving the problems in the above-mentioned conventional techniques, and the semiconductor wafer is particularly chamfered at the peripheral portion. In the applied semiconductor wafer, the chamfered shape has a pair of inclined surfaces formed on the front and back surfaces of the semiconductor wafer so as to gradually go inward in the thickness direction as going outward in the radial direction. A curved surface that connects the outer ends of the respective inclined surfaces, and the curved surface extends from the central portion in the thickness direction toward the front and back surfaces of the semiconductor wafer, and
A second for smoothly connecting the first curved surface to each of the inclined surfaces
Curved surface of the first curved surface having a second radius of curvature
It is characterized in that it is formed to be larger than the radius of curvature of the curved surface.
「作用」 本発明に係わる半導体ウエハは、大きな曲率半径の第１
の湾曲面によって、半導体ウエハの面方向の外力を受け
て該外力の分散を図り、また、第２の湾曲面によって、
前記外力の作用点近傍における半導体ウエハの外周面を
円滑な曲面となすものである。"Operation" The semiconductor wafer according to the present invention has the first large radius of curvature.
The curved surface of the semiconductor wafer receives an external force in the surface direction of the semiconductor wafer to disperse the external force, and the second curved surface of
The outer peripheral surface of the semiconductor wafer near the point of application of the external force is a smooth curved surface.
「実施例」 以下、発明の一実施例を第１図に基づき説明する。[Embodiment] An embodiment of the present invention will be described below with reference to FIG.
第１図は、本実施例の要部を示すもので、図中符号５は
半導体ウエハである。FIG. 1 shows an essential part of the present embodiment, in which reference numeral 5 is a semiconductor wafer.
該半導体ウエハ５は、直径Ｄが125mm、厚さＷが0.625mm
の円板形状であって、その表裏面６・７の周縁部に、半
径方向外方にいくにしたがい漸次厚さ方向内方へ向かう
ように一対の傾斜面８・９を形成するとともに、これら
の各傾斜面８・９の外方端部間を連絡する湾曲面10とを
形成し、かつ、該湾曲面10を、前記厚さ方向中心部から
半導体ウエハ５の表裏面に向かって延びる第１の湾曲面
11と、該第１の湾曲面11を前記各傾斜面８・９へ滑らか
に連絡する第２の湾曲面12とによって形成し、前記第１
の湾曲面11の曲率半径R1を第２の湾曲面12の曲率半径R2
よりも大きく形成した概略構成となっている。The semiconductor wafer 5 has a diameter D of 125 mm and a thickness W of 0.625 mm.
And a pair of inclined surfaces 8 and 9 are formed at the peripheral edges of the front and back surfaces 6 and 7 so as to gradually inward in the thickness direction as they go outward in the radial direction. A curved surface 10 that connects between the outer ends of the inclined surfaces 8 and 9 of the inclined surface 8 and the curved surface 10 that extends from the central portion in the thickness direction toward the front and back surfaces of the semiconductor wafer 5. 1 curved surface
11 and the second curved surface 12 that smoothly connects the first curved surface 11 to each of the inclined surfaces 8 and 9, and
The radius of curvature R 2 of curvature radius R 1 of the curved surface 11 of the second curved surface 12
It has a schematic configuration that is larger than the above.
次いでこれらの詳細について説明すれば、前記傾斜面８
・９は、その延長線と半導体ウエハ５の表裏面６・７と
によって形成される挾角（θ）が約11°となるように形
成されている。この角度は、バイポーラIC用に設定され
たもので、MOS・IC用では、22°が採用される。Next, these will be described in detail.
9 is formed such that the included angle (θ) formed by the extension line and the front and back surfaces 6 and 7 of the semiconductor wafer 5 is about 11 °. This angle is set for bipolar ICs, and 22 ° is adopted for MOS ICs.
前記第１の湾曲面10の曲率半径R1は、半導体ウエハ５の
厚さＷの1/3倍〜1.5倍の範囲内で設定することが好まし
く、本実施例では0.5mmに設定されており、その中心が
半導体ウエハ５の厚さ方向の中間部に設定されている。The radius of curvature R 1 of the first curved surface 10 is preferably set within a range of 1/3 to 1.5 times the thickness W of the semiconductor wafer 5, and is set to 0.5 mm in this embodiment. The center thereof is set at the middle portion of the semiconductor wafer 5 in the thickness direction.
前記第２の湾曲面12の曲率半径R2は、0.1mm〜0.3mmの範
囲内で設定することが好ましく、本実施例では、0.2mm
ないし0.21mmに設定されており、その中心は、前記曲率
半径R2によって形成される湾曲面12が、前記第１の湾曲
面11および傾斜面８・９に連続するような位置に設けら
れている。The radius of curvature R 2 of the second curved surface 12 is preferably set within a range of 0.1 mm to 0.3 mm, and in the present embodiment, 0.2 mm.
To 0.21 mm, the center of which is provided at a position such that the curved surface 12 formed by the radius of curvature R 2 is continuous with the first curved surface 11 and the inclined surfaces 8 and 9. There is.
そして、前述したような半導体ウエハ５は、砥石によっ
て前記傾斜面８・９を切削したのちに、第１の湾曲面11
を切削し、次いで、第２の湾曲面12を切削することによ
って形成される。Then, in the semiconductor wafer 5 as described above, after cutting the inclined surfaces 8 and 9 with a grindstone, the first curved surface 11 is cut.
Is formed, and then the second curved surface 12 is cut.
このように形成された本実施例の半導体ウエハ５の強度
について、従来の半導体ウエハＳとの比較を行なったと
ころ、表−１に示す結果が得られた。When the strength of the semiconductor wafer 5 of this example formed in this way was compared with that of the conventional semiconductor wafer S, the results shown in Table 1 were obtained.
ａ）試験条件 半導体ウエハ５（Ｓ）を垂直に保持しておき、該半導体
ウエハ５（Ｓ）の直上から重りを落下させて、半導体ウ
エハ５（Ｓ）の周縁部に衝突させ、半導体ウエハ５
（Ｓ）に欠けが発生するまでの衝突回数によって比較し
た。a) Test conditions The semiconductor wafer 5 (S) is held vertically, and a weight is dropped from directly above the semiconductor wafer 5 (S) to collide with the peripheral edge of the semiconductor wafer 5 (S), and the semiconductor wafer 5
The comparison was made by the number of collisions until chipping occurred in (S).
また、前記重りは、縦×横×高さが2.8mm×7mm×12mm
で、重量を2gとし、さらに、半導体ウエハ５との衝突面
に半円筒状の超硬チップを埋め込んだ構成のものを用い
た。Also, the weight has a length x width x height of 2.8 mm x 7 mm x 12 mm.
The weight was set to 2 g, and a semi-cylindrical cemented carbide chip was embedded in the collision surface with the semiconductor wafer 5.
ｂ）比較例−１ 第２図の従来例に対応して、直径125mm、厚さ0.625mmの
円板の表裏面周縁部に、曲率半径0.16mmないし0.20mmの
湾曲面１・２を形成して面取りを行なった半導体ウエハ
Ｓ。b) Comparative Example-1 Corresponding to the conventional example of FIG. 2, curved surfaces 1 and 2 having a radius of curvature of 0.16 mm to 0.20 mm are formed on the peripheral portions of the front and back surfaces of a disk having a diameter of 125 mm and a thickness of 0.625 mm. A semiconductor wafer S chamfered.
ｃ）比較例−２ 比較例−１の湾曲面１・２の曲率半径を0.25mmないし0.
27mmとした半導体ウエハＳ。c) Comparative Example-2 The radius of curvature of the curved surfaces 1 and 2 of Comparative Example-1 is 0.25 mm to 0.
27 mm semiconductor wafer S.
ｄ）比較例−３ 第３図の従来例に対応して、直径125mm、厚さ0.625mmの
円板の周縁部を楕円形状に形成するに際し、長径部の最
小曲率半径を0.25mmとした半導体ウエハ。d) Comparative Example-3 A semiconductor in which the minimum radius of curvature of the long diameter portion was 0.25 mm when forming the peripheral portion of a disk having a diameter of 125 mm and a thickness of 0.625 mm into an elliptical shape, corresponding to the conventional example of FIG. Wafer.
以上の結果から明らかなように、本実施例の半導体ウエ
ハ５においては、従来の半導体ウエハＳに比べてほぼ２
倍以上の衝撃強度が得られた。 As is clear from the above results, the semiconductor wafer 5 of the present embodiment is almost 2 times larger than the conventional semiconductor wafer S.
More than twice the impact strength was obtained.
このように耐衝撃性能の向上が図れるのは、半導体ウエ
ハ５の面方向の外力に対する受圧面として働く第１の湾
曲面11が大きな曲率半径によって形成されて、受圧面積
が拡大されていること、また、第２の湾曲面12および傾
斜面８・９の作用により、受圧部分の近傍から角部が除
去されているとともに、第１の受圧面11に加わった外力
が円滑に分散されること等によるものと考えられる。As described above, the impact resistance can be improved because the first curved surface 11 that functions as a pressure receiving surface against an external force in the surface direction of the semiconductor wafer 5 is formed with a large radius of curvature, and the pressure receiving area is enlarged. Further, by the action of the second curved surface 12 and the inclined surfaces 8 and 9, the corners are removed from the vicinity of the pressure receiving portion, and the external force applied to the first pressure receiving surface 11 is smoothly dispersed. It is thought to be due to.
なお、前記実施例において示した細部の寸法は一例であ
って、設計要求等に基づき種々変更可能である。It should be noted that the dimensions of the details shown in the above embodiment are examples, and can be variously changed based on design requirements and the like.
「発明の効果」 以上説明したように、本発明に係わる半導体ウエハは、
周縁部に面取りが施された半導体ウエハであって、前記
面取りの形状が、半導体ウエハの表裏面に、半径方向外
方にいくにしたがい漸次厚さ方向内方へ向かうように形
成された一対の傾斜面と、これらの各傾斜面の外方端部
間を連絡する湾曲面とによって形成され、かつ、各湾曲
面が、前記厚さ方向中心部から半導体ウエハの表裏面に
向かって延びる第１の湾曲面と、該第１の湾曲面を前記
各傾斜面へ滑らかに連絡する第２の湾曲面とを備え、前
記第１の湾曲面の曲率半径が第２の湾曲面の曲率半径よ
りも大きく形成されていることを特徴とするもので、大
きな曲率半径の第１の湾曲面によって、半導体ウエハ周
端部に作用する面方向の外力を受けて該外力の分散を図
り、また、第２の湾曲面によって、前記外力の作用点近
傍における半導体ウエハの外周を円滑な曲面となすとと
もに、第１の湾曲面に作用する前記外力を、第２の湾曲
面および傾斜面を介して円滑に分散させて、耐衝撃性能
を大幅に向上させることができる等の優れた効果を奏す
る。"Effects of the Invention" As described above, the semiconductor wafer according to the present invention is
A semiconductor wafer having a peripheral edge chamfered, wherein a shape of the chamfer is formed on the front and back surfaces of the semiconductor wafer so as to gradually go inward in the thickness direction as going outward in the radial direction. A first curved surface extending from the center portion in the thickness direction toward the front and back surfaces of the semiconductor wafer, the first curved surface being formed by the inclined surface and the curved surface connecting the outer end portions of these inclined surfaces. Curved surface and a second curved surface that connects the first curved surface to each of the inclined surfaces smoothly, and the radius of curvature of the first curved surface is greater than the radius of curvature of the second curved surface. The first curved surface having a large radius of curvature receives an external force in the surface direction that acts on the peripheral edge portion of the semiconductor wafer to disperse the external force. Due to the curved surface of the semiconductor, the semiconductor near the point of application of the external force The outer periphery of the roof can be formed into a smooth curved surface, and the external force that acts on the first curved surface can be smoothly dispersed through the second curved surface and the inclined surface to significantly improve impact resistance performance. It has excellent effects such as being able to.
図面中、第１図は本発明の一実施例を示す要部の縦断面
図、第２図および第３図はそれぞれ従来の半導体ウエハ
を示す縦断面図である。 ５……半導体ウエハ、６……表面、７……裏面、８・９
……傾斜面、10……湾曲面、11……第１の湾曲面、12…
…第２の湾曲面。In the drawings, FIG. 1 is a longitudinal sectional view of an essential part showing an embodiment of the present invention, and FIGS. 2 and 3 are longitudinal sectional views showing a conventional semiconductor wafer, respectively. 5 ... Semiconductor wafer, 6 ... Front surface, 7 ... Back surface, 8.9
…… Inclined surface, 10 …… Curved surface, 11 …… First curved surface, 12…
… Second curved surface.
Claims (3)
あって、前記面取りの形状が、半導体ウエハの表裏面
に、半径方向外方にいくにしたがい漸次厚さ方向内方へ
向かうように形成された一対の傾斜面と、これらの各傾
斜面の外方端部間を連絡する湾曲面とによって形成さ
れ、かつ、該湾曲面が、前記厚さ方向中心部から半導体
ウエハの表裏面に向かって延びる第１の湾曲面と、該第
１の湾曲面を前記各傾斜面へ滑らかに連絡する第２の湾
曲面とを備え、前記第１の湾曲面の曲率半径が第２の湾
曲面の曲率半径よりも大きく形成されていることを特徴
とする半導体ウエハ。1. A semiconductor wafer having a chamfered peripheral edge, wherein the chamfered shape is formed so that the front and back surfaces of the semiconductor wafer gradually go inward in the thickness direction as going outward in the radial direction. It is formed by a pair of formed inclined surfaces and a curved surface that connects between the outer ends of these inclined surfaces, and the curved surface extends from the thickness direction central portion to the front and back surfaces of the semiconductor wafer. A first curved surface extending toward the first curved surface; and a second curved surface that smoothly connects the first curved surface to each of the inclined surfaces, and the radius of curvature of the first curved surface is the second curved surface. A semiconductor wafer having a radius of curvature larger than that of the semiconductor wafer.
記半導体ウエハの厚さの３分の１ないし1.5倍の範囲内
で設定されていることを特徴とする特許請求の範囲第１
項記載の半導体ウエハ。2. The radius of curvature of the first curved surface is set within a range of one-third to 1.5 times the thickness of the semiconductor wafer. 1
A semiconductor wafer according to item.
mないし0.3mmの範囲内で設定されていることを特徴とす
る特許請求の範囲第１項記載の半導体ウエハ。3. The radius of curvature of the second curved surface is 0.1 m.
The semiconductor wafer according to claim 1, wherein the semiconductor wafer is set within a range of m to 0.3 mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61106293A JPH079873B2 (en) | 1986-05-09 | 1986-05-09 | Semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61106293A JPH079873B2 (en) | 1986-05-09 | 1986-05-09 | Semiconductor wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62263626A JPS62263626A (en) | 1987-11-16 |
| JPH079873B2 true JPH079873B2 (en) | 1995-02-01 |
Family
ID=14430004
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61106293A Expired - Fee Related JPH079873B2 (en) | 1986-05-09 | 1986-05-09 | Semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH079873B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101470723B1 (en) * | 2010-05-19 | 2014-12-08 | 가부시끼가이샤 구레하 | Process for production of polyarylene sulfides, and polyarylene sulfides |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52155968A (en) * | 1976-06-19 | 1977-12-24 | Fujitsu Ltd | Semiconductor wafer and its production |
| JPS58100432A (en) * | 1981-12-11 | 1983-06-15 | Hitachi Ltd | Bevelling process of wafer |
| JPS5980934A (en) * | 1983-09-16 | 1984-05-10 | Nec Corp | Manufacture for semiconductor device |
| JPS59107520A (en) * | 1982-12-13 | 1984-06-21 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor substrate |
-
1986
- 1986-05-09 JP JP61106293A patent/JPH079873B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52155968A (en) * | 1976-06-19 | 1977-12-24 | Fujitsu Ltd | Semiconductor wafer and its production |
| JPS58100432A (en) * | 1981-12-11 | 1983-06-15 | Hitachi Ltd | Bevelling process of wafer |
| JPS59107520A (en) * | 1982-12-13 | 1984-06-21 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor substrate |
| JPS5980934A (en) * | 1983-09-16 | 1984-05-10 | Nec Corp | Manufacture for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62263626A (en) | 1987-11-16 |
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