JPS59105738A - Packet address system - Google Patents

Abstract

PURPOSE:To always limit the number of comparators to one regardless of the number of address registers by selecting one of plural address registers through a partial field of address information within a packet. CONSTITUTION:The packet address information is divided into two fields F1 and F2. The addres registers are selected in the field F1, and the field F2 is defined as an actual comparison address. It is also possible to divide the packet address information into >=3 fields to have address registers of various levels. That is, the packet address information is divided into at least 2 parts and the address registers are selected in one of those two fields. The information of the F1 is used to the input of a multiplexer M, and as a result one of (n) units of address registers, e.g., a register AR1 is selected. In this case, the address comparison is executed between the register AR1 selected at the multiplexer M and the field F2.

Description

Detailed Description of the Invention (a) 0 Technical Field of the Invention The present invention relates to an address determination method for a packet transmitting/receiving device in packet switching, and particularly relates to a method for determining an address for a packet transmitting/receiving device in packet switching, and particularly for a packet that specifies a plurality of addresses per device for the packet transmitting/receiving device. -Relates to addressing methods.

(World), Prior Art and Problems Figure 1 is a block diagram showing an example of a conventional packet addressing method. In the figure, ARI, AR2...ARn are address registers, and C1, C2...Cn are address registers. Each of them is a comparison circuit, OR is an OR gate, and F is packet address information from a packet.

As shown in Figure 1, in conventional packet switching),
A plurality of address registers and one comparison circuit are attached to each of the address registers in the packet transmitting/receiving device, and each address register is attached to each of the address registers.
A method is used in which four registers compare at the same time, but according to this conventional method, in order to specify n addresses per device, n address registers and n comparison circuits are required. This has the disadvantage that the circuit configuration becomes complicated.

(C)9 Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art;
By providing a packet addressing method in which the number of comparison circuits is always one regardless of the number of address registers by selecting one of a plurality of address registers according to some fields of address information in a packet. be.

(d) 8 Structure of the Invention According to the present invention, the above object is achieved by comprising a plurality of address registers and a comparison circuit on the receiving side of a packet transmitting/receiving device, and a plurality of fields for storing packet address information. a plurality of the address registers are selected according to the first section of the field, the selected address register occupies the comparison circuit, and the comparison circuit divides the address registers into the second section of the field and below. This is achieved by providing a packet addressing scheme characterized by comparing contained packet address information with a selected address register.

(e) 0 Embodiment of the invention FIG. 2 is a block diagram showing an embodiment of the invention. In the figure, API, AR2...A Rn are address registers, C is a comparison circuit, M is a multiplexer, Fl , F2
represents a field containing packet address information.

The present invention will be described in detail below with reference to FIG.

In this embodiment, the packet address information is divided into two fields (Fl, F2), the address register is selected in field F1, and the field F2 is used as the actual comparison address.

Note that a multi-level address register with three or more fields may be provided, but the key point is to divide the packet node address information into at least two parts, and use one part, or field, to register the address register. It is about making choices.

The information in field F1 becomes an input to multiplexer M, so that one address register, for example ARI, is selected from n address registers. The address comparison is then performed between the selected address register in multiplexer M, in this case ARI and field F2.
It is carried out between.

At this time, only the selected address register is connected to the comparison circuit C, and the other address registers cannot be connected to the comparison circuit C because they are inhibited from being connected to the comparison circuit C.

After the address comparison is completed, the inhibition of the comparator circuit C is released and the next address comparison is started.

(f) 8. Effects of the Invention As explained in detail above, according to the present invention, only one comparator circuit is used for lightning, regardless of the number of address registers used, which simplifies the circuit. It has a big effect on measuring.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional packet addressing method. In the figure, ARI, AR2...ARn are address registers, C1, C2...Cn are comparison circuits, and OR is an OR register. The gate and F are bucket-node address information from the packet. FIG. 2 is a program diagram showing one embodiment of the present invention. In the figure, ARI, AR2, . . . ARn are address registers, C is a comparison circuit, M is a multiplexer, Fl, F2
represents a field containing packet address information.

Claims (1)

[Claims] A receiving side of a packet transmitting/receiving device is equipped with a plurality of address registers and a comparison circuit, and a field accommodating packet address information is divided into a plurality of fields, and a first section of the field is used to divide the plurality of addresses into a plurality of fields. - Select a register, and the selected address register occupies the comparison circuit, and the comparison circuit compares the packet address information stored in the second section and below of the field with the selected address register. A packet addressing method characterized by comparing.