JPS59105565A - Electric field detecting circuit - Google Patents

Electric field detecting circuit

Info

Publication number
JPS59105565A
JPS59105565A JP21652582A JP21652582A JPS59105565A JP S59105565 A JPS59105565 A JP S59105565A JP 21652582 A JP21652582 A JP 21652582A JP 21652582 A JP21652582 A JP 21652582A JP S59105565 A JPS59105565 A JP S59105565A
Authority
JP
Japan
Prior art keywords
circuit
electric field
voltage
output
variable attenuator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21652582A
Other languages
Japanese (ja)
Inventor
Kenji Mizoe
溝江 謙司
Hiroyuki Fukushima
弘之 福島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP21652582A priority Critical patent/JPS59105565A/en
Publication of JPS59105565A publication Critical patent/JPS59105565A/en
Pending legal-status Critical Current

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  • Monitoring And Testing Of Transmission In General (AREA)

Abstract

PURPOSE:To contrive to enlarge the dynamic range of an electric field detecting circuit, by comparing detection output voltage corresponding to the electric field passing through a voltage shift circuit with reference voltage to subject an input variable attenuator and the voltage shift circuit to feed-back control. CONSTITUTION:The electric field detection signal passing a variable attenuator 3 comes to electric field detection output voltage good in linearity through a logarithm amplifier 1, a detector circuit 2 and a voltage shift circuit 6. On the other hand, this detection output voltage is compared to reference voltage by a comparator 5 to subject the attenuator 3 and the circuit 6 to feed-back control through a memory circuit 4 for temporarily storing the comparison result and electric field detection good in linearity is performed without using a multi- stage logarithmic amplifier circuit to make it possible to attain to enlarge the dynamic range of an electric field detecting circuit.

Description

【発明の詳細な説明】 本発明は通信機器及び測定器等の電界情報を得るために
挿入される電界検出回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electric field detection circuit inserted into communication equipment, measuring instruments, etc. to obtain electric field information.

従来、この種の電界検出回路は、入力信号を対数増幅す
る対数増幅器とこの対数増幅器の出力を検波する検波回
路とにより構成されている。この対数増幅器を多段接続
することによシ、この対数増幅器の対数特性の直線性の
向上をはかっていたが、この多段接続は入力信号周波数
が高くなると異常発振を起こし易く、そのため接続数に
限度があり、ダイナミックレンジも特定の大きさ以下に
ならざるをえなかった。
Conventionally, this type of electric field detection circuit includes a logarithmic amplifier that logarithmically amplifies an input signal and a detection circuit that detects the output of the logarithmic amplifier. By connecting these logarithmic amplifiers in multiple stages, the linearity of the logarithmic characteristics of this logarithmic amplifier has been improved. However, this multi-stage connection tends to cause abnormal oscillation when the input signal frequency becomes high, so there is a limit to the number of connections. , and the dynamic range had to be below a certain level.

本発明の目的は、このような従来の欠点を除去し、ダイ
ナミックレンジを大幅に拡大できる電界検出回路を提供
することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide an electric field detection circuit that can eliminate such conventional drawbacks and greatly expand the dynamic range.

本発明の電界検出回路は、入力信号を第1の制御信号に
より減衰させる可変減衰器と、この可変減衰器の出力を
増幅する増幅器と、この増幅器の出力を検波して直流電
圧を出力する検波器表、この検波器の出力電圧を第2の
制御信号によりシフトする電圧77ト回路と、この電圧
シフト回路の出力電圧全所定基準電圧と比較する比較回
路と、この比較回路の出力を一時記憶する記憶回路と、
この記憶回路の出力により前記第1および第2の制御信
号をそわぞれ形L11iシ前記可変沖衰器および前記電
圧シフト回路を段階的に制御する制御手段とを含み構成
される。
The electric field detection circuit of the present invention includes a variable attenuator that attenuates an input signal using a first control signal, an amplifier that amplifies the output of the variable attenuator, and a detector that detects the output of the amplifier and outputs a DC voltage. a voltage circuit that shifts the output voltage of this detector by a second control signal, a comparison circuit that compares all output voltages of this voltage shift circuit with a predetermined reference voltage, and a temporary memory for the output of this comparison circuit. A memory circuit that
It is configured to include a control means for controlling the variable attenuator and the voltage shift circuit in a step-by-step manner by respectively controlling the first and second control signals L11i based on the output of the storage circuit.

以下図面により本発明の詳細な説明する。The present invention will be explained in detail below with reference to the drawings.

第1図は従来の電界検出回路のブロック図であり、対数
増幅器1とろ波回路2とを縦続接続して構成される。第
3図ta+にその入出力特性図を示す。
FIG. 1 is a block diagram of a conventional electric field detection circuit, which is constructed by connecting a logarithmic amplifier 1 and a filter circuit 2 in cascade. FIG. 3 ta+ shows its input/output characteristic diagram.

すなわち、入力信号レベルがB(dBμ)の時出力信号
レベルはI)(vl 、 C(dRμ)の時E(v)で
あり、入力信号変化量FdB(=C−By対して出力信
号がりニアな範囲はE −1)(vlであった。
That is, when the input signal level is B (dBμ), the output signal level is I) (vl), and when C (dRμ), it is E (v), and the output signal is nearer to the input signal change amount FdB (=C-By). The range was E-1)(vl).

第2図は本発明の実施例の電界検出回路のブロック図で
あ)、従来のものよ92倍のダイナミックレンジを得ら
れるように設定した場合について説明する。まず、入力
信号は可変減衰器3を通った後、対数増幅器1に加わる
が可変減衰器3の初期状態の減衰葉音0としておく。こ
の対数増幅器lの出力は検波回路2に加わり、この検波
回路2において直流電圧に変換される。この直流常圧は
電圧シフト回路6に加わるが、この電圧シフト回路6を
その一!まの値で通ル抜けるように、電圧フット回路6
の初期状態の設定電圧’kO(Vlとする。
FIG. 2 is a block diagram of an electric field detection circuit according to an embodiment of the present invention), and a case will be described in which settings are made to obtain a dynamic range 92 times that of the conventional circuit. First, the input signal is applied to the logarithmic amplifier 1 after passing through the variable attenuator 3, but the initial state of the variable attenuator 3 is set to zero. The output of this logarithmic amplifier l is applied to a detection circuit 2, where it is converted into a DC voltage. This DC normal pressure is applied to the voltage shift circuit 6, and this voltage shift circuit 6 is one of them! Voltage foot circuit 6
The initial state setting voltage 'kO (Vl) is assumed to be 'kO (Vl).

一方、電圧シフト回路6の出力はコンパレータ(比較D
o路)5に加わる。このコンパレータ5の基準電圧L(
v)は、対数増幅器lが飽和領域となる直前の入力信号
レベルC(dBμ)を検波回路2により検波した時の出
力信号レベルE (vlに設定しておく。このコンパレ
ータ5の出力情報により記憶回路4の出力が所定の減衰
量F’(dB)になるように可変減衰器3を制御すると
同時に電圧/フト回路6の設定電圧’t−0(Vlから
F(v)に制御する。したがって、入力信号レベルがC
(dBμ)より大きいレベルで入力された場合には、検
波回路2の出力では第3図(blに示すような従来と同
等な特性になるが、電圧ソフト回路6の出力では電圧E
(v)だけンフトされ、第3図(c)に示すようなダイ
ナミックレンジの広い対数特性が得られることになる。
On the other hand, the output of the voltage shift circuit 6 is connected to a comparator (comparison D
o path) joins 5. The reference voltage L of this comparator 5 (
v) is the output signal level E (set to vl) when the input signal level C (dBμ) just before the logarithmic amplifier l reaches the saturation region is detected by the detection circuit 2. It is stored using the output information of the comparator 5. The variable attenuator 3 is controlled so that the output of the circuit 4 becomes a predetermined attenuation amount F' (dB), and at the same time, the set voltage of the voltage/foot circuit 6 is controlled from 't-0 (Vl to F(v)). , the input signal level is C
(dBμ), the output of the detection circuit 2 has the same characteristics as the conventional one as shown in FIG. 3 (bl), but the output of the voltage soft circuit 6 shows the voltage E
(v), and a logarithmic characteristic with a wide dynamic range as shown in FIG. 3(c) is obtained.

本実施例の説明から明らかなように、従来の電界検出回
路では入力信号変化量F(dB)(=C−B)に対して
リニアな出力信号変化量はE −D(vlだけであった
が、本実施例では入力信号変化量2F(dB)(*H−
B)に対してリニアな出力信号変化量がG−D(−i=
2(E−D))(V)まで伸びて約2倍のダイナミック
レンジが得られる。
As is clear from the description of this embodiment, in the conventional electric field detection circuit, the amount of change in the output signal that is linear with respect to the amount of change in the input signal F (dB) (=C-B) is only E - D (vl). However, in this example, the input signal change amount is 2F (dB) (*H-
The amount of linear output signal change with respect to B) is GD(-i=
2(E-D))(V), resulting in approximately twice the dynamic range.

なお、本実施例では、ダイナミックレンジを2倍に広け
る例で説明したが、コンパレータ5をさらに追加して可
変減衰器3の減衰量及び電圧シフト回路6の設定電圧を
さらに可変できるようにしておけば、記憶回路4の出力
情報により、さらにダイナミックレンジを広けることが
できる。
Although this embodiment has been described as an example in which the dynamic range is doubled, a comparator 5 is further added to make it possible to further vary the attenuation amount of the variable attenuator 3 and the set voltage of the voltage shift circuit 6. By doing so, the dynamic range can be further widened by the output information of the memory circuit 4.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電界検出回路のブロック図、第2図は本
発明の一実施例のブロック図、第3図(alは従来の電
界検出回路の入出力特性図、第3図(b)は本実施例の
検波回路における入出力特性図、第3図(C1は本実施
例の全体の入出力特性図である。 5− 図において、 1・・・・・・対数増幅器、2・・・・・・検波回路、
3・・・・・・可変減衰器、4・・・・・・記憶回路、
訃・・・・・コンパレータ、6・・・・・・電圧シフト
回路 である。 6− −2入力′佑号ルベ)しくdBIL)       □
λ乃]シ号レしベ(df$)(α)         
   (4)第3図 →^Qアp?にレヘ)L/(dBF、)(C)
Fig. 1 is a block diagram of a conventional electric field detection circuit, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 (al is an input/output characteristic diagram of a conventional electric field detection circuit, Fig. 3(b) is an input/output characteristic diagram of the detection circuit of this embodiment, and FIG. 3 (C1 is an input/output characteristic diagram of the entire embodiment of this embodiment.) ...detection circuit,
3...variable attenuator, 4...memory circuit,
6: Comparator, 6: Voltage shift circuit. 6--2 input 'Yu No. dBIL) □
λno] Shi No. Level (df$) (α)
(4) Figure 3 → ^Qap? nirehe)L/(dBF,)(C)

Claims (1)

【特許請求の範囲】[Claims] 入力信号を第1の制御信号によシ減衰させる可と、この
検波器の出力電圧を第2の制御信号によりシフトする電
圧シフト回路と、この電圧シフト回路の出力電圧を所定
基準電圧と比較する比較回路と、この比較回路の出力を
一時記憶する記憶回路と、この記憶回路の出力によシ前
記第1および第2の制御信号をそれぞれ形成し前記可変
減衰器および前記電圧シフト回路を段階的に制御する制
御手段とを含む電界検出回路。
a voltage shift circuit that shifts the output voltage of the detector according to a second control signal, and compares the output voltage of the voltage shift circuit with a predetermined reference voltage. a comparator circuit; a memory circuit for temporarily storing the output of the comparator circuit; and a memory circuit for forming the first and second control signals, respectively, from the outputs of the memory circuit and controlling the variable attenuator and the voltage shift circuit in stages. and a control means for controlling the electric field detection circuit.
JP21652582A 1982-12-09 1982-12-09 Electric field detecting circuit Pending JPS59105565A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21652582A JPS59105565A (en) 1982-12-09 1982-12-09 Electric field detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21652582A JPS59105565A (en) 1982-12-09 1982-12-09 Electric field detecting circuit

Publications (1)

Publication Number Publication Date
JPS59105565A true JPS59105565A (en) 1984-06-18

Family

ID=16689790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21652582A Pending JPS59105565A (en) 1982-12-09 1982-12-09 Electric field detecting circuit

Country Status (1)

Country Link
JP (1) JPS59105565A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013508689A (en) * 2009-10-16 2013-03-07 エンプリマス,インク. Electromagnetic field detection system and method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5147464A (en) * 1974-10-21 1976-04-23 Onkyo Sokuki Kk RENJIJIDOSEIGYOHOSHIKI

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5147464A (en) * 1974-10-21 1976-04-23 Onkyo Sokuki Kk RENJIJIDOSEIGYOHOSHIKI

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013508689A (en) * 2009-10-16 2013-03-07 エンプリマス,インク. Electromagnetic field detection system and method

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