JPS59104870A - Driving circuit of solid-state image pickup device - Google Patents

Abstract

PURPOSE:To prevent malfunction of a driving circuit by waveform-shaping a pulse deciding the starting time of a pulse driving a horizontal transferring means by a pulse frequency-divided from a master clock. CONSTITUTION:The master clock fM from an oscillating circuit 11 is received by a 1/2 frequency divider 12 and a 1/7 frequency divider 13, and a 2MHz pulse being an output of the divider 13 is inputted to a 1/130 frequency divider 14 and a phiHCLR clock circuit 30. The output of the circuit 14 is inputted to a vertical synchronizing pulse generating circuit 16 and a horizontal synchronizing pulse generating decoder 15. The circuit 16 generates a vertical synchronizing pulse group, and the circuit 15 generates a horizontal synchronizing pulse group and outputs a phiHCLR pulse, which is inputted to the circuit 30. The circuit 30 outputs the phiHCLRL pulse less in the phase change to the clock fM by waveform-shaping the phiHCLR pulse by the 2MHz pulse again and the phiHCLRL pulse is inputted to the circuit 12. Thus, the circuit 12 outputs a horizontal transfer pulse group phiH without producing a shift of pulse from the clock fM and the phiHCLRL pulse.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a drive circuit for a solid-state imaging device.

(Conventional structure and its problems) Solid-state image sensors have various features not found in conventional image pickup tubes, such as small size, light weight, and long life. It is expected to be used as a robot vision sensor and an industrial camera. System reliability is important for both home video cameras and industrial cameras.Industrial cameras in particular may be used under harsh conditions, so extreme reliability is essential. Become something. The reliability of a camera can be divided into the reliability of the solid-state image sensor and the drive circuit that drives it.

Figure 1 shows the conventional CPD (Charge Primin)
g Device) type solid-state imaging device, the imaging section has an MO6 type structure, and includes a photodiode 1, a vertical shift register 2, an interlace circuit 3, and an M
It consists of an OS switch 4, vertical signal lines 5, a horizontal transfer section 6 consisting of a 4-phase CCD, and a vertical/horizontal conversion section 7.

To drive this CPD type solid-state image sensor, the interlace circuit 3 is driven, the pulse φF and the vertical shift register 2 are started, and the vertical ik1 period pulse group of the /F pulse SP and the vertical shift register 2 are driven. Driving the pulse φV and the vertical/horizontal converter 7 ・Horizontal synchronizing pulse group of the Cruz TG, and further driving the horizontal transfer unit 6 consisting of a 4-phase CCD A cis group is required. All of these pulse groups are generated by dividing the master clock FM, which is the basis of the entire system.

Figure 2 shows the configuration of a drive circuit for a conventional CPD type solid-state image sensor, in which 11 is an oscillation circuit, 12 is a divide-by-2 circuit, and 1
3 is a frequency divider circuit by 7, 14 is a frequency divider by 130 circuit, 15 is a horizontal synchronization pulse generation decoder, 16 is a vertical synchronization pulse generation circuit, 17 is a horizontal operation pulse group, 18 is a horizontal synchronization pulse group, 19 indicates the vertical synchronization group.

The oscillation circuit 11 oscillates to the master clock, and 14.31818 MHz is selected as the master clock fM in order to make the output of the solid-state image pickup device conform to the standard TV SOON system and create a drive signal. One of the outputs of this oscillation circuit 11 is input to a divide-by-2 circuit 12, and the other is input to a divide-by-7 circuit J3 for generating 2MHz pulses used to generate the horizontal synchronizing pulse group 18, and then to a divide-by-7 circuit J3. The output 2 MHz pulse of 13 is input to the 130 frequency divider circuit 14, and its output is input to the horizontal synchronization pulse generation decoder 15. The horizontal synchronization pulse group 28 and the horizontal transfer pulse group 17 (φH
1 to φH4), which determines the starting position, is output. This φHCLR-e Rus is Sarani 2
The signal is input to the frequency divider circuit 12, and the frequency divider circuit 12 outputs a four-phase horizontal transfer signal group]7 (φH1 to φH4) from the master clock fM and φHCLR-e.

Further, the output of the 130 frequency divider circuit 14 is input to the vertical synchronization i44 pulse generation circuit 6 to generate the vertical synchronization IE pulse group 19. The driving pulse for the CPD solid-state image sensor is generated in the above manner.

FIG. 3 shows details of the divide-by-two circuit 12 shown in FIG.

As already mentioned, this divide-by-2 circuit uses the master clock f
This circuit obtains a 4-phase horizontal transfer signal group 17 (φH1 to φH4) from the input of the output φHCLR pulse of the horizontal synchronization signal generation decoder 15 shown in FIG. -FF') 21 and 22.

JK-FF 22 is similar to JK-FF21 as shown in the figure.
The output terminals Q and σ of are connected to the terminals J and , respectively, and are completely locked to the JK-FF 21, so only the operation of the JK-FF 21 will be described here.

In JK-FF 21, the master clock fM is input to the cK terminal, and at the falling edge of this master clock fM, the states of the output terminals Q and Q are inverted, and the output of the output terminal Q is inverted. As the horizontal transfer signal φH1, the output of the output terminal is used as the horizontal transfer signal φH3. The outputs of output terminals Q and Q of the JK-FF 22 are used as horizontal transfer pulses φH2 and φH4, respectively. J.K.
When a low-level signal is input to the R terminal of the -FF, the output terminals Q and 2 of the JK-FF are reset to a low level and a high level, respectively. Utilizing this, when the φI (CLR pulse) is input to the R terminal of this JK-FF 2 ], a reset is applied and the start position of the horizontal transfer pulse group (φH1 to φH4,) is determined. By inputting the square (5) tough lock f'H'+ φ1 (CLR-e pulse to the CK terminal and R terminal of ?', a 4-phase horizontal transfer/gusus group is obtained.

FIG. 4 shows clock timing showing the operation of the horizontal transfer/gurus generation circuit.

Here, the phase difference T between the rising edge of φHCLR and the rising edge of master clock 7 fM is as shown in FIG. 14, horizontal synchronization) It shows the phase difference between the delay time from the master clock fM caused by the generation through the P shift generation decoder 15 and the nearest rising edge of the master clock fM.

If this phase difference T is always constant, the horizontal transfer pulse φ
The start time of H1 remains the same. However, φHC
The LR pulse is divided by 7 from the master clock fM in the circuit 13.
．． 130 frequency divider circuit 14, horizontal synchronization/signal generation decoder] 5, the phase difference T fluctuates due to temperature changes in the delay time of each circuit.

In other words, the cumulative temperature change (6) of the phase lag of each circuit with respect to the master clock until φHCLR is generated appears as the temperature change of the phase of φHCLR with respect to the master clock. This phase difference T increases as the temperature rises, and the next falling edge of the master clock 1. When the horizontal transfer pulse φH1 exceeds φH1 as shown in the figure, the horizontal transfer pulse φH1
It will be in the form of /. In other words, due to fluctuations in the phase difference T, the start position of the horizontal transfer pulse changes instantaneously or
After going through a transient state for a certain period of time, it moves backward by one clock of the master clock. Similarly, when the phase difference T decreases due to temperature drop and exceeds the falling edge t2 before the master clock fMO, the horizontal transfer phase φH1 becomes φl(1// in FIG. 3). When the movement of this horizontal transfer pulse is observed on a monitor screen, the image moves horizontally in an instant or after a period of transition. When a camera system using a solid-state image sensor is used for computer processing, especially in industrial measurement, if this phenomenon occurs due to temperature, it may lead to misrecognition. (7) Unsuitable as a camera.

(Object of the Invention) An object of the present invention is to solve the above-mentioned difficulties and eliminate malfunctions of the drive circuit.

The above-mentioned horizontal transfer or malfunction due to the movement of the pulse φH is caused by φH.
Since the movement of CLR-ξrus due to temperature is the cause, it is sufficient to eliminate this movement due to temperature. Therefore, what can be considered is the horizontal synchronization pulse generation decoder 1 in Fig. 2.
5 or φ) (Reshaping the CLR pulse with one that has no phase change due to temperature or one that has very little phase change.

(Configuration of the Invention) FIG. 5 is a block diagram of an embodiment showing the configuration of a driving circuit for a CPD type solid-state image sensor according to the present invention, in which 11 is an oscillation circuit, 12 is a frequency divider circuit, and 13 is a frequency divider circuit by 7. circuit, 14 is 1
30 frequency divider circuit, 15 is a horizontal synchronization pulse generation decoder,
16 is the vertical synchronization/P pulse generation circuit shown in the same way as in Fig. 2, φHCLR lock circuit 30.
It is distinctive in that it has been established.

(8) (Description of Embodiment) The φHCLR lock circuit 30 uses the φHCLR norm which is the output of the horizontal synchronization norm generation decoder 15, and the 2M) Iz norm which is the output of the divide-by-7 circuit 13. This is a circuit that inputs φHCTJRL7'e and outputs φHCTJRL7'e.
The HCLRL pulse is the φHCLR pulse reshaped with a 2 MHz pulse.

Considering the 2 MHz /9 pulse output from the divide-by-7 circuit 13 and the phase of the master clock fM, the 2 MHz Noculus passes only through the divide-by-7 circuit 13, and is completely synchronized with the master clock 8. , and the phase change due to temperature is much smaller than that of φHCLR''.

By reshaping the φHCLR pulse with this 2 MHz i4 pulse, a φHCLRL with very little phase change with respect to the master clock fM due to temperature changes can be obtained, which allows horizontal transfer/? Luz no longer moves.

FIG. 6 is a clock timing diagram showing the operation of one embodiment of the drive circuit of the present invention.
L pulse, 2 MHz Noculus, horizontal transfer Noculus φ
The relationship of H1 is shown.

(9) Rising edge tl of master clock fM Nearby, for the reason mentioned above, the phase of φHCLR changes greatly depending on the temperature, and ① Hill/Grus moves by 1 bit with respect to the master clock. However, master black, Riku's start-up Lueno t
3, the master clock fM and 2 MHz/'
There is almost no change due to the temperature of the liquid, so this 2 Ml
(z) There is almost no phase change between the φHCT and RL pulses reshaped by the f pulse and the master clock fM, and malfunctions of the horizontal transfer pulse generation divide-by-2 circuit 12 do not occur.

The present invention can be applied not only to a CPD type solid-state developing device, but also to a drive circuit for an interline type CCD % frame transfer CCD and an MO8 solid-state image pickup device.

In addition, in the present invention, 2M is required for locking φHCT and H.
Although the Hz pulse is used, other frequency divided clocks with less change in phase difference from the master clock may be used, and the same effect can be obtained in this case as well.

(Effects of the Invention) As explained above, according to the present invention, φHCLR(1
0) By adopting a drive circuit for a CPD type solid-state image sensor using a circuit, it can be used only in the range of -10°C to 60°C due to the above-mentioned malfunction when using a conventional φHCLR. The IC temperature guarantee range is 40°C to 85°C.
There is no malfunction at all in a temperature range that sufficiently covers ℃. Therefore, the present invention has the advantage that the operating temperature range of the solid-state camera is expanded and that it can be used as an industrial camera under severe temperature conditions. be.

[Brief explanation of the drawings] Fig. 1 is a diagram showing the structure of a conventional CPD type solid-state image sensor;
Figure 2 is a diagram showing the configuration of a drive circuit for a conventional CPD type solid-state image sensor, Figure 3 is a diagram showing details of the divide-by-2 circuit shown in Figure 2, and Figure 4 is a diagram of the horizontal transfer pulse generation circuit. A clock timing diagram showing the operation, FIG. 5 is a block diagram of an embodiment showing the configuration of a driving circuit for a CPD type solid-state image sensor according to the present invention, and FIG. 6 shows an operation of an embodiment of the driving circuit of the present invention. FIG. 3 is a clock timing diagram. DESCRIPTION OF SYMBOLS 1... Photodiode, 2... Vertical shift reno star, 3 - Interlace circuit, 4... MOS switch, 51. Vertical signal line, 6...Horizontal transfer unit, 7...Vertical/horizontal conversion unit, 11 - Oscillation circuit, 12...2 frequency division circuit, 13...7 frequency division circuit, 14...130 frequency division circuit,
15・Horizontal synchronization pulse generation decoder, 16...Vertical synchronization pulse generation circuit, 17・Horizontal transfer/gusis group, 1
8・Horizontal synchronization・♀sis group,]9・Vertical synchronization pulse group, 21.22-JK flinoff flonop, 30・φH
CLR lock circuit. Figure 1 6H Figure 2 Figure 3

Claims (1)

[Claims] It includes a plurality of photoelectric conversion sections, vertical transfer means for vertically transferring the signal charges converted by the photoelectric conversion sections, and horizontal transfer means for horizontally transferring the signal charges transferred by the vertical transfer means. A driving circuit for a solid-state imaging device, characterized in that a pulse that determines a start time of a driving pulse for driving the horizontal transfer means is shaped into a pulse frequency-divided from a master clock. .