JPS59104825A - Signal synthesizing circuit - Google Patents

Abstract

PURPOSE:To attain high speed by processing simultaneously two analog signals on real time and to simplify the device by reducing the storage capacity. CONSTITUTION:Analog input signals S1, S2 are inputted from input terminals IN1, IN2 and applied to temporary storage circuits MC1-MC4. An output of the temporary storage circuits MC1, MC2 is applied to a subtraction circuit SC1 and an output of temporaty storage circuits MC3, MC4 is applied to a subtraction circuit SC2, an effective value of analog input signals S1, S2 is obtained respectively. The respective effective value is applied to a switching circuit SW2, and the effective value of the analog input signals S1, S2 is outputted alternately from an output terminal in the timing of a timing signal CLK for detection.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog signal synthesis circuit.

Conventionally, in order to combine two analog signals, which have a reference level and a data level alternately and whose phases differ by a period of one cycle, into a single signal using the effective difference value between the data level and the reference level, first one of them is The reference level and data level of the other analog signal are sequentially converted into analog/digital (hereinafter abbreviated as AD conversion) and stored in a storage device as digital values.The reference level and data level of the other analog signal are then sequentially converted into AD The signal was converted and stored in the storage device as a digital value, all valid values were calculated by the controller, and the valid values of both signals were alternately inserted to form one numerical string. However, with this method, both signals cannot be processed simultaneously, so it takes twice as long as VC to process all the two signals, and the signal processed later is the second signal, so the reproducibility is poor. becomes a problem. Furthermore, in order to store two signals, one for the reference level and the other for the data level, the storage device needs to have a large storage capacity.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal synthesis circuit for solving all of the above problems.

According to the present invention, two signals can be processed at the same time, and only valid values can be extracted as a complete series of signals, so that reproducibility does not become an issue and thicker signals are also effective in terms of high-speed processing.

EMBODIMENT OF THE INVENTION Hereinafter, one embodiment of the present invention will be specifically described with reference to all the drawings.

Figure 1 shows the analog input signals 81, 82 and the detection timing signal CLK. As shown in the figure, the two VC analog input signals 81, 82 have a reference level RF and a data level T)T', and are out of phase with each other. They are different by half a cycle. Figure 2 shows a conventional signal synthesizer, in which the analog input signal S'
l, S2'Th input terminal INI.

Input from IN2 and switch circuit SWI I+? : What is the input signal? The analog value is converted into a digital value by the AD converter AD and stored in the storage device MUvc. Since all the values stored once are subtracted and rearranged by the controller CTVrcJ, this is disadvantageous in terms of speeding up.

In the signal synthesis circuit according to the embodiment of the present invention shown in FIG. 3, analog input signals 81. S2'e input terminal INI, I
Input from N2, temporary memory circuit MCI.

Supplied to MC2, MC3, and MC4. temporary memory circuit MC
I.

The MC4 stores all values at the timing of the detection timing signal CLK and holds them until the next timing.

The temporary storage circuits MC2 and MC3 store the values at the timing when the detection timing signal CLK-e and the inversion circuit IVVC, r: are inverted, and hold the values until the next timing. The outputs of the temporary memory circuits MCI and MC2 are sent to the subtraction circuit SC.
I to obtain the valid value of the analog input signal S1. Further, the outputs of the temporary storage circuits MC3 and MC4 are supplied to a subtraction circuit SC2, and the effective value of the analog input signal S2 is obtained. The valid values of analog input signals S1 and 82 are:
The valid values of the analog input signals sl and 82 are supplied to the switching circuit SW2, and are alternately outputted from the output terminal OUT at the timing of the detection timing signal CLK.

As described above, according to the VC1 signal synthesis circuit of the present invention, two analog signals can be processed simultaneously in real time, and high speed processing can be achieved. Further, even if the output values of the signal synthesis circuit of the present invention are stored in a storage device, the storage capacity can be significantly reduced compared to the conventional method, and the device can be simplified.

[Brief explanation of the drawing]

FIG. 1 shows an analog input signal and a timing signal for detection, FIG. 2 shows a conventional signal synthesis device, and FIG. 3 shows a signal synthesis circuit of the present invention. In the figure, 81.82...analog input signal, ■V...
...Inverting circuit, CLK...timing signal for detection, OUT'...output terminal, RF...
Reference level, DT...Data level, INI,
IN2...Input terminal, SWI, SW2...
・Switching circuit, AD...Analog-digital converter, MV...Storage device, CT...Controller, MCI, MC2, MC3, MC4...
・Temporary memory circuit, 8C1°SC2...Subtraction circuit. 5- 1st Zuko? mouth

Claims (1)

[Claims] In a circuit which receives as input an analog signal having a reference level and a data level alternately, and an analog signal having a reference level and a data level alternately, the phase of which is mistaken by half a cycle from that analog signal, the analog signal has a reference level and a data level alternately. has two sets of temporary storage circuits and subtraction circuits for fully storing the data level and the reference level and calculating the difference;
A signal synthesis circuit whose purpose is to combine the outputs of a set of subtraction circuits into a single signal by alternately outputting them.