SU151511A1 - Method of performing logical operations - Google Patents

Description

In the known methods of performing logical operations using ferrite shift registers, the prohibition operation is performed either by logic signals or clock signals. This leads to the fact that, on the one hand, the signals of the logic cells and the cells of the memory must satisfy all the requirements imposed on the inhibitory signals, and on the other hand, the inhibitory signals in this case vary greatly depending on the load cells and how they run these cells. There have been attempts to eliminate these disadvantages by introducing two types of memory cells, with the output signals of one cell being prohibiting for another cell. Such a complication of the scheme does not, however, give the desired result.

According to the proposed method, special standard signals are used as prohibiting signals, the parameters of which are chosen so that they can prohibit any signal of memory cells.

and "or.

We will show that using the "memory," or "blocking" recording of the "1 in the cell" of the memory with a standard signal, you can perform logical operations of the form:

7 Е; rW Е 7 and II. X

1 (X); 1 (n} t L (K) J.

FIG. 1 and 2. Circuits are introduced that implement the operations of ia a-b (a. B signals) by the proposed method.

The signals a p b can be logical sums of signals of the same tact, i.e., arriving during the same clock cycle. Conventional clock (synchronizing) signals denoted by the letter t, standard-f. The numbers on the bottom right of the symbols indicate in what sequence (at what time) the signals a, b, t and t ° should be given.

№151511-2

The clock signals t and standard signals / ° are generated by a circuit controlling the operation of the entire computing device.

At the output of the cell / cell, the signal from the m-signal may appear either at the time of arrival of the signal b, or signal c. “O on condition that before this a signal a comes to the input of cell 1. The output signal, simultaneously with U2, is equivalent to operation a. & and simultaneous with 4 is equivalent to the operation a-b. If the standard signal tz ° coincides with the logical signal b, then the signal C2 corresponding to the operation a.b, is prohibited from writing "1 to cell 2, and the signal C3 corresponding to operation a. B, the entry "1 in cell 2" is permitted. Thus, the output is a signal corresponding to the operation a. 6 or in general:

If the standard 4 ° signal coincides in phase with the clock signal, then cell 2 is recorded as "1, the corresponding operation a. B or in general:

(SA-WSn

(X)) (y)).

It should be noted that the standard signals serve only to prohibit the recording of “1 in a cell” of memory. To write off, "1 uses the clock signals and sipnals of the" memory and "or" cells. And since the state of the last one is less than the time when the recording “1 in the cell” of the memory “is prohibited”, the power of the standard signal can be much less than the power of the signals of the cell “frame or” or. This makes it possible to create standard signal generators with a higher load capacity.

Subject invention

Method of performing logical operations of the type (i V X VVXn) V

ACi.VF VVyj or (X, VX, VV X,) f (Y, V Y,

where n and t are the number of logical inputs, characterized in that, in order to increase the reliability of operation of logic devices, a series of standard ban signals are supplied to their inputs synchronously with the clock signals, the parameters of which block the variation of the input signal parameters.

jS) (Sr

(X) 1 (y))

23455 Tanta

t-

2

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