JPS59104119A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59104119A
JPS59104119A JP21522982A JP21522982A JPS59104119A JP S59104119 A JPS59104119 A JP S59104119A JP 21522982 A JP21522982 A JP 21522982A JP 21522982 A JP21522982 A JP 21522982A JP S59104119 A JPS59104119 A JP S59104119A
Authority
JP
Japan
Prior art keywords
polycrystalline silicon
gas
silicon layer
ratio
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21522982A
Other languages
Japanese (ja)
Inventor
Seiichiro Kawamura
河村　誠一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21522982A priority Critical patent/JPS59104119A/en
Publication of JPS59104119A publication Critical patent/JPS59104119A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C23C16/0272—Deposition of sub-layers, e.g. to promote the adhesion of the main coating
    • C23C16/029—Graded interfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Optics & Photonics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To form a stable and favorable (silicon on insulator) construction at a semiconductor device by a method wherein the ratio of mixed gas for chemical vapor phase growth is controlled on time, the silicon oxide film of the prescribed thickness is formed at first, and the ratio of silicon is increased gradually to grow a polycrystalline silicon layer continuously. CONSTITUTION:An SiO2 film 21 is grown on a semiconductor substrate 12. At a point in time when thickness of SiO2 grows to the degree of 5,000Angstrom , the prescribed mixing ratio of NO gas to SiH4 gas is reduced gradually for the prescribed hours, and after a middle layer 22 constructed by increasing gradually the ratio of the Si component is formed, supply of NO gas is stopped. According to thermal decomposition of SiH4 gas, a polycrystalline silicon layer 23 is grown continuously. Then by seepingly irradiating a CWAr laser beam 24, a silicon single crystal layer 25 is formed by conversion from the polycrystalline silicon layer 23.

Description

【発明の詳細な説明】 （ａ）　　発明の技術分野 不発明は半導ｔｉｆ−装置の製造方法に係り、特に絶縁
膜とに多結晶シリコン層を単結晶化する（　５ｉｄｉ−
ＣＯｎ　Ｏｎ　Ｉｎ５ｕｌａｔｏｒ　）　工程に２ける
化学気相成長法の改善に関するものでるる。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The invention relates to a method for manufacturing a semiconductor TIF-device, and in particular to a method for manufacturing a semiconductor TIF-device, in which a polycrystalline silicon layer is made into a single crystal with an insulating film (5idi-
Concerning improvements in the chemical vapor deposition method in the second step (CON On Inverter).

（ｂ）　　技術の背景 ｒｌＪｃｆルイｂニルＳ　ＯＩ：　（５ｉ１１ａｏｎ　
ｏｎ工ｎ５ｕｌａｔｏｒ）構造は素子の三次元回路など
のＶＬＳＩの基礎となる技術として注目を集めている。(b) Technical background rlJcf Louis bnil SOI: (5i11aon
The on-engine 5ulator) structure is attracting attention as a fundamental technology for VLSI such as three-dimensional circuits of elements.

（Ｃ）　　従来技術と間萌点 従来の５ＯＩｉ造においては、第１図に示すごとくシリ
コン基板ｌ、ヒに酸化又は化学気相成長法（ＣＶＤ法）
によってシリコン酸化膜２を全面に被覆し、該シリコン
酸化膜２上にＣＶＤ法によって所定厚の多結晶シリコン
層８を形成した後、該多結晶シリコン層ａｈを連続アル
ゴンレーザービーム（ＣＷ　Ａｒ　Ｌａ５ｅｒ　Ｂｅａ
ｍ　）　　４　（Ｄ掃引照射によって、該多結晶シリコ
ン禮８を前記シリコン酸化膜２土に単結晶化させている
。(C) The difference between the conventional technology and the point of development In the conventional 5OI structure, as shown in Fig. 1, the silicon substrate is oxidized or chemical vapor deposition (CVD).
After forming a polycrystalline silicon layer 8 of a predetermined thickness on the silicon oxide film 2 by the CVD method, the polycrystalline silicon layer ah is treated with a continuous argon laser beam (CW Ar La5er Bea).
m) 4 (The polycrystalline silicon layer 8 is made into a single crystal in the silicon oxide film 2 by D sweep irradiation.

しかしながらＬ記し−ザービーム４を照射して多結晶シ
リコン層８を単結晶化する際に、レーザービーム４の出
力の強さによって従来方法においてハ、多結晶シリコン
−８とシリコン酸化１庚２の異質の両物質が接触する界
面に介在する自然酸化膜や、両物質間の熱云尋、応力、
ぬれなどの相違ン単結晶層５とｆ地のシリコン酸化膜２
とが剥離する現象があり、ｖ３縁躾」−における単結晶
化の大きな問題点となっていた。However, when the polycrystalline silicon layer 8 is single-crystalized by irradiating the polycrystalline silicon layer 8 with L-marked laser beam 4, due to the intensity of the output of the laser beam 4, in the conventional method, C. natural oxide film intervening at the interface where the two materials come into contact, heat exchange between the two materials, stress,
Differences in wetting, etc. between the single crystal layer 5 and the silicon oxide film 2
There was a phenomenon in which the crystals peeled off, which was a major problem in single crystallization in V3 Enjitsu.

（ｄ）　　発明の目的 本発明の目的は、かかる問題点ケ解消するためなされた
もので、シリコン酸化膜と多結晶シリコン祠の曲に介在
する自然酸化膜の発生を防Ｉヒ１７、かつシリコン酸化
膜と多結晶シリコン層の間に連続してなる中間層を設け
ることによって安定して良好なＳＯ丁構造金形成１〜つ
る半導体装｛尚の製造方法の提供にある。(d) Purpose of the Invention The purpose of the present invention was to solve these problems and to prevent the formation of a natural oxide film interposed between the silicon oxide film and the curve of the polycrystalline silicon An object of the present invention is to provide a method for producing a semiconductor device having a stable and good SO structure by providing a continuous intermediate layer between an oxide film and a polycrystalline silicon layer.

（ｅ）発明の構成 その目的を達成するため、本発明は基板北の絶縁膜に、
多結晶シリコン幀を形成し、該多結晶シリコン籾を単結
晶化する半導体装置の製造方法でリコン比率を増加し連
続して多結晶シリコン層を成長する工程が含まれてなる
ことを特徴とするものである。(e) Structure of the Invention In order to achieve the object, the present invention provides an insulating film on the north side of the substrate.
A method for manufacturing a semiconductor device in which a polycrystalline silicon layer is formed and the polycrystalline silicon grain is made into a single crystal, and the method includes a step of increasing the recon ratio and continuously growing a polycrystalline silicon layer. It is something.

以Ｆ本発明の実施例について図面全参照して説明する。Hereinafter, embodiments of the present invention will be described with reference to all the drawings.

第３図は本発明を実施するためのＣＶ　Ｉ）装置の概略
構成図、第４図及び第５図は本発明の一火施例を説明す
るための工程警部断面図であり前回と同等の部分につい
ては同−符号全件している。第３図においてＣＶＤ装置
ｌＯは反応１ｉＶｌｌ内に半導体基板１２を載置するサ
セプター１３、該ザセブター１３−ｈの半導体基板１２
全加熱する加熱装置１４が付設され、該基板１２を所望
温度に加熱調整するＩ４構を有している。又前記反応管
Ｉ【内にｔ尾ばＩグ応ガスを導入するための導入管１５
が設けられ、複数の反応ガスの流績孕調整するだめのカ
ス流量−調整器１６．１７が付設されている。Fig. 3 is a schematic configuration diagram of a CV I) device for implementing the present invention, and Figs. 4 and 5 are sectional views of a process inspector for explaining a one-fire embodiment of the present invention, and are similar to the previous one. All parts have the same sign. In FIG. 3, the CVD apparatus IO includes a susceptor 13 for placing a semiconductor substrate 12 in a reaction 1iVll, and a semiconductor substrate 12 in the susceptor 13-h.
A heating device 14 for total heating is attached, and has an I4 structure for heating and adjusting the substrate 12 to a desired temperature. Also, an introduction pipe 15 for introducing reaction gas into the reaction tube I
is provided, and waste flow rate regulators 16 and 17 for adjusting the flow rate of a plurality of reaction gases are attached.

かかる装置をｌ旧いて半キネ昨基板１２ヒに初めに絶縁
膜たとえばシリコン酸化映ケ代侵し、連続して多結晶シ
リコン−を形成する場合には、Ｒ１１記反応ｙｔｔ内の
サセプター１３）Ｈに半導体基板１２を載置し、加熱装
置１４によって所望ｌ晶度たとえば６５０’１２に核基
板１２を、７．１１１熱し前記ガス導入管１５よりＳｉ
Ｈ４ガス及びＮＯガヌを規定幇調整ＷＡＩＬ１７によっ
て混隙して反応管ｌｌ内に導入し、丁を己の熱化学反応
式 ％式％ によ、って第４図に示した如く半Ｉ４体基板１２）にシ
リコン酸化膜（５ｉｎ２）　２１が成長する。所望のシ
リコン酸化膜厚約５０００人成長した時、侭で前記ＮＯ
ガスのＳｉＨ４ガスに対する規定混隆比を調整器１７を
用いて所足時間除々に減少させてＳｊ−成分比が除々に
増加してなる中間や１２２を形成した後、ＮＯガスの供
給を調整器１７により厚化すればＳｉＨ４ガスの熱分解
により多結晶シリコン層２８が連続して成長し、所望の
膜厚に達した時点で反応を酪化すれば図ボし／ζように
半導体基板１２とに成長したシリコン酸化膜２１．ヒに
連続してシリコンが除々に増加してなる中間層２２に引
続いて多結晶シリコン層２３が形成される。旧記ＮＯガ
ス減少率は所望のシリコン酸化膜厚に応じて変えればよ
く、又多結晶シリコン層２Ｂの成長を黒度させでもよい
。かかる構造の半導体基板１２に第５図に示すとと（Ｃ
ＷＡｒレーザービーム２４を掃引照射することによって
、前記多結晶シリコン層２３をシリコン酸化膜２１　Ｊ
：にけ１結晶化させシリコン単結晶層２５を形成する。When such an apparatus is old and an insulating film, for example, silicon oxide, is first eroded onto the half-finished substrate 12 and polycrystalline silicon is successively formed, the susceptor 13) in the reaction Ytt of R11 is heated. The semiconductor substrate 12 is mounted, and the core substrate 12 is heated to a desired crystallinity, for example, 650'12, by the heating device 14, and Si is then heated through the gas introduction pipe 15.
H4 gas and NO gas are mixed with each other by the specified adjustment WAIL17 and introduced into the reaction tube 11, and the mixture is converted into a half I4 body according to the thermochemical reaction formula % as shown in Figure 4. A silicon oxide film (5in2) 21 is grown on the substrate 12). When the desired silicon oxide film thickness has grown to about 5,000, the NO.
After gradually decreasing the specified mixing ratio of the gas to SiH4 gas for a sufficient period of time using the regulator 17 to form an intermediate ratio 122 in which the Sj-component ratio gradually increases, the supply of NO gas is adjusted using the regulator 17. If the thickness is increased by 17, the polycrystalline silicon layer 28 will grow continuously by thermal decomposition of SiH4 gas, and when the desired film thickness is reached, the reaction will be oxidized to form the semiconductor substrate 12 as shown in the figure/ζ. The silicon oxide film 21. A polycrystalline silicon layer 23 is formed following the intermediate layer 22 in which the silicon content is gradually increased. The aforementioned NO gas reduction rate may be changed depending on the desired thickness of the silicon oxide film, or the growth of the polycrystalline silicon layer 2B may be made darker. When a semiconductor substrate 12 having such a structure is shown in FIG.
By sweeping and irradiating the WAr laser beam 24, the polycrystalline silicon layer 23 is transformed into a silicon oxide film 21J.
: Crystallize the silicon layer 25 to form a silicon single crystal layer 25.

かかる場α、前述したようにシリコン酸化膜２１と多結
晶シリコン−２３は連続して成長されているため、従来
方法におけるシリコン酸化膜２１と多結晶シリコン層２
Ｂとの界面に放置などによる自然酸化膜の発生は見られ
ず、又シリコン酸化膜２１と多結晶シリコン層２３の異
質の両物質の界面には連続した緩衝領域の中間層２２の
存在によって熱伝導、応力、ぬれなどの相違ケ緩和しＣ
Ｗ　Ａｒレーサーヒーム２４の照射によって単結化する
場合のシリコン酸化膜２１と単結晶層２５の剥離を防止
することが４能となる。In such a case α, since the silicon oxide film 21 and the polycrystalline silicon layer 23 are grown continuously as described above, the silicon oxide film 21 and the polycrystalline silicon layer 2 in the conventional method are
No natural oxide film was observed at the interface between the silicon oxide film 21 and the polycrystalline silicon layer 23 due to the presence of the intermediate layer 22, which is a continuous buffer region. Alleviates differences in conduction, stress, wetting, etc.
The fourth function is to prevent the silicon oxide film 21 and the single crystal layer 25 from peeling off when they are singulated by irradiation with the WAr laser beam 24.

（ｇ）発明の効果 以」−説明したごとく本発明によれば絶縁暎會化字気相
成長するに際し、該化学気相１ｉｔ（長用混αガ連続し
て多結晶シリコン層を成長することによって、＠！３縁
ＩＩ側と多結晶シリコン層の中間に緩衝領域ケ設け、多
結晶シリコン層をｔｌ結晶化する際の界面に２ける剥離
の現象を防止し、安定して良好なＳＯ工槽構造形成が可
能となり品′ａ向ヒ９歩留向上による原価低減に大きな
効果がある。尚本実施例は本発明の一例としてあげたも
のであり本発明の範囲を制御頒するものではない。(g) Effects of the Invention - As explained, according to the present invention, when performing insulating vapor phase growth, a polycrystalline silicon layer is continuously grown in the chemical vapor phase (long-term mixed α layer). By providing a buffer region between the @!3 edge II side and the polycrystalline silicon layer, it is possible to prevent the phenomenon of peeling at the interface during TL crystallization of the polycrystalline silicon layer, and to achieve a stable and good SO process. It is possible to form a tank structure, which has a great effect on cost reduction by improving product yield.This example is given as an example of the present invention and is not intended to control or distribute the scope of the present invention. .

【図面の簡単な説明】[Brief explanation of the drawing]

第１図及び第２図は従来方法を説、明するための工稈要
部断面図、第３図は本発明を実施するためのＣＶＤ装置
の概略構成図、第４図及び第５図は本発明の一矢施例を
説明するだめの工程警部断面図である。 図において１．１．２は坐導陣ノ、（板、２，２１はシ
リコン酸化１１ψ、８．２３は多結晶シリコン層、５．
２５は小結晶化したシリコン単結晶層、２２は中間１田
を示す。 ８９−1 and 2 are sectional views of essential parts of a culm for explaining and clarifying the conventional method, FIG. 3 is a schematic configuration diagram of a CVD apparatus for carrying out the present invention, and FIGS. 4 and 5 are FIG. 2 is a sectional view of a process inspection section for explaining an embodiment of the present invention. In the figure, 1.1.2 is a zadojin (plate), 2 and 21 are silicon oxide 11ψ, 8.23 is a polycrystalline silicon layer, and 5.
25 is a small-crystal silicon single crystal layer, and 22 is an intermediate layer. 89-

Claims (1)

【特許請求の範囲】[Claims] 基板との絶縁膜に、多結晶シリコン層紫形成し、該多結
晶シリコン層を単結晶化する半導体装置の製造方法であ
って、前記絶縁膜を化学気相成長するに際し、該化学気
相成長法混きガヌ比を時間的に調整し、初めに所定厚の
シリコン酸化膜を形成し、漸次シリコン比率を増加し、
連続して多結晶シリコン層を成長する工程が含まれてな
ることを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device in which a polycrystalline silicon layer is formed on an insulating film with a substrate, and the polycrystalline silicon layer is made into a single crystal. By temporally adjusting the mixing Ganu ratio, a silicon oxide film of a predetermined thickness is first formed, and the silicon ratio is gradually increased.
A method for manufacturing a semiconductor device, comprising the step of continuously growing a polycrystalline silicon layer.
JP21522982A 1982-12-07 1982-12-07 Manufacture of semiconductor device Pending JPS59104119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21522982A JPS59104119A (en) 1982-12-07 1982-12-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21522982A JPS59104119A (en) 1982-12-07 1982-12-07 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59104119A true JPS59104119A (en) 1984-06-15

Family

ID=16668841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21522982A Pending JPS59104119A (en) 1982-12-07 1982-12-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59104119A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57178317A (en) * 1981-04-27 1982-11-02 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor single crystal

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57178317A (en) * 1981-04-27 1982-11-02 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor single crystal

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