JPS59103482A - Automatic slice circuit - Google Patents

Abstract

PURPOSE:To set automatically a clock line signal as a slice level by detecting a horizontal scanning period where a character information signal of a text multiplex broadcasting signal is superimposed, extracting the clock line signal of the character information signal during the period and obtaining the average value. CONSTITUTION:A video signal on which the character information signal is superimposed is clamped to a prescribed DC potential at a clamp circuit 22, inputted to one input of a comparator 25 and applied to a switch 26. The switch 26 is turned on by a pulse P6 only a period on which the clock line signal CR is superimposed during the horizontal scanning period on which the character information signal is superimposed, the signal CR passing through the switch 26 is applied to a filter 27, the average value is detected and the DC voltage is applied to the other input of the comparator 25 as it is via an impedance converting circuit 28 as a slice voltage. Even if the amplitude of the character information signal is changed, the optimum slice level is obtained at all times.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an automatic slicing circuit for separating a text information signal from a teletext broadcasting signal [Technical Background of the Invention] Teletext broadcasting systems originally A signal indicating text information is superimposed on the television broadcast signal of This is a system that displays images on the screen. FIG. 1 is a circuit diagram showing a conventional circuit for separating a text information signal from a teletext broadcast signal. A video signal including a character information signal as shown in FIG. 2(a) is applied to the terminal 11. The character information signal is generally superimposed on any horizontal scanning period of the IOHth to 21st horizontal scanning periods of the vertical blanking period. A clock run-in signal CR indicating a reference phase is present at the beginning of the character information signal. A signal processing circuit that performs predetermined signal processing on the text information signal DK separated from the video signal generates a pulse synchronized with the clock run-in signal CR, and samples the text information signal using this pulse.

A framing code FC exists after the clock run-in signal CR. The framing code FC is used to synchronize frames of character information signals. After this framing code FC, actual data such as character data, character data, color code data, and control data exists. These data are taken into the signal processing circuit for the first time when the framing code FC is detected.

A video signal on which such text information signals are superimposed is
The signal from terminal 1 is supplied to a reference lamp circuit 12 and a synchronous separation circuit 13. By the synchronous separation circuit 13, the K
The horizontal synchronization signal HD is separated as shown. This horizontal synchronization signal HD is transmitted to two stages of monostable multivibrators 14, 1.
5 to the superposition position @ of the color burst signal CB. This delayed signal is supplied to the clamp circuit 12 as a clamp pulse Pc. This clamp pulse Pc is shown in FIG. 2(c). The video signal supplied to the clamp circuit 12 is clamped (DC constrained) to a DC level determined by the variable resistance circuit VR, during the period of the clamp pulse Pc. The DC reproduced video signal can be supplied to one input terminal of the comparator 16.

The comparator 16 separates the text information signal from the video signal by a semi-fixed DC level determined by the variable resistance circuit VR. This slice level ■8 is placed on the 2nd floor.
21(a) shows the separated character information signal in FIG. 2(d).
).

[Problems with background technology]

However, in the case of the above configuration, since the slice level Vs is semi-fixed, when the amplitude of the video signal, especially the amplitude of the text information signal, changes, the slice level Vs is adjusted appropriately to a non-optimal level by the variable resistance circuit VR. There was a circuit and a woman that was very difficult for Koza to use.

3- [Object of the Invention] This invention was made in order to deal with the above-mentioned situation, and even if the amplitude of the text information signal changes, the optimum slice level is always automatically set and the video signal and text can be processed. The object is to provide an automatic slicing circuit capable of separating information signals.

[Summary of the invention]

This invention detects a horizontal scanning period in which a character information signal is superimposed, extracts the clock run-in signal of the character information signal during this detected horizontal scanning period, calculates its average value, and slices this average value. The video signal and the text information signal are separated as levels.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 3, a video signal on which a character information signal is superimposed is applied to terminal 2. This video signal is not supplied to the clamp circuit 2, the oscillation circuit 23, and the sync separation circuit 24. 4- The video signal DC-regenerated by the clamp circuit 22 is supplied to one input terminal of the comparator 25, and is also supplied to the switch circuit 26. Supply increases. The switch circuit 26 is turned on during the horizontal scanning period when the character information signal is superimposed, and only at the position where the clock run-in signal CR is superimposed. Clock run-in signal CR passed through switch 26
is supplied to the filter 27. This filter 27 consists of a capacitor C5 and a resistor R. The capacitor C is charged and discharged according to the level of the clock run-in signal CR, thereby detecting the average value of the clock run-in signal CR. This average value output is supplied to the impedance conversion circuit 28. The impedance conversion circuit 28 is configured to receive the average value output at high impedance and output it at low impedance. This impedance conversion circuit 28
The output voltage is supplied to the other input terminal of the comparator 25 as a slice voltage. The circuits 22, 25-28 are the automatic slicing circuits and the core.

The oscillation circuit 23 outputs an oscillation signal of 3.58 MHz (color subcarrier frequency f8θ) synchronized with the color burst signal CB. Clock run-in signal C for character information signal
A sampling pulse SP synchronized with R is output. The serial/parallel conversion shift register 30 samples the character information signal output from the comparator 25 with a sampling pulse SP, and converts, for example, 8 bits into 1 byte of parallel data.

A framing code detection circuit 31 supplies a detection pulse P to the write address generation circuit 32 when the framing code FC is detected from the output of the shift register 30. The write address generation circuit 32 is reset by the detection pulse P and driven by the sampling pulse SP. The output data of the shift register 30 is stored in 9.9K RAM, and in this case,
The write address generation circuit 32 generates data for specifying addresses in bytes. The line counter 34 is reset by the vertical synchronization signal VDK separated by the synchronization separation circuit 24, and counts the horizontal synchronization signal HD. By taking in RAM,?
,? Data for specifying the address of the character information signal in units of one horizontal scanning period is supplied to the character information signal. The 35-bit horizontal synchronization signal IID is used as a reset pulse, and the sampling pulse is used as a clock input. The count output of this bit counter 35 is supplied to a decoder 36. The decoder 36 generates a burst gate pulse P, which is used as a clamp pulse in the clamp circuit 22 and also as a gate pulse for supplying a color burst signal to the oscillation circuit 23. 1, this decoder 36 generates a gate pulse P of the clock run-in signal CR and supplies it to the AND circuit 37. The decoder 38 inputs the data from the line counter 34 and generates a load pulse P4 for the parallel-to-serial conversion shift register 39.

A horizontal synchronizing signal i (D) is used as a clock input to the shift register 39. The Ilo port 40 latches data set by the CPU 41 and supplies this data to the shift register 39 in the form of parallel data. The AND circuit calculates the logical product of the vyFi gate pulse P3 and the output pulse P of the shift register 39, and performs the above operation.

A CPU 4 outputs a switch pulse P for controlling off.
1 specifies the address of the capture RAM 33 according to the program in the program ROM 4z, reads out data stored in the capture RAM 33, and performs predetermined signal processing.

The calculation RAM 4.9 is a 0 system state buffer 4 used for temporarily storing the calculation results of the CPU 41.
9 to 48 take in the output data of the shift register 30 R
A.M.? , 9 and when the stored data is read out and subjected to predetermined signal processing by the CPU 41, the data bus L)B and address designation AB are switched. A signal P for this switching is output from the decoder 38, and a signal obtained by inverting this signal by an inverter 49 is supplied to the state buffers 46 to 48 as a switching signal. Note that 49 is a display memory, 50 is a pattern φ color decoder, and 51 is an output interface circuit.

The operation in the above configuration will be explained. First, the text information signal separated from the video signal is subjected to predetermined processing,
I will briefly explain the operation of supplying the picture tube. character ff1
When a report is taken into the RAM 33, the syntate buffers 43 to 45 open their gates, and the syntate buffers 46 to 48 close their gates. Intake RAM33
The opposite is true when reading more data.

In this case, the system state buffers 43 to 45 open their gates during the period from the IOHth to the 21<1>th period when a character information signal may exist, and the system state buffers 46 to 4sFi open their gates.
Gates open during other periods.

First, when the character information signal is taken into the loading RAM 5s, the character information signal separated from the video signal by the comparator 25 is supplied to the shift register 30. In this shift register 30, the character information signal is sampled using a sampling pulse SP and is converted into parallel data consisting of 1 byte of 8 bits, for example. The framing code detection circuit 3 detects the framing code FC from the output data of the shift register 30 and outputs a detection pulse P1. This detection pulse P
sf) "4 to h", address designation data in rebyte units is output from the honor read address generation circuit 32, and the data in the shift register 30 is taken in to a predetermined address in the take-in RAM 33.In this case, the character information signal is 1
Addressing data for each packet and one horizontal scanning period is outputted from the line outputter 34.

Next, take in RAM, 9. ? The data imported into CP
read according to addressing data from U4J,
The data is taken into the calculation RAM 41.9.

The data loaded into the calculation RAM 4.9 is the program RO.
It undergoes predetermined signal processing according to the program of M42.

That is, if the data is control data, predetermined control is performed accordingly. If the data is text or character data, it is supplied as pattern data to a display memory (not shown). If it is color code data, it is supplied to the display memory 49 as color data.

Image data such as pattern data and color data taken into the display memory are transferred to the R axis 5GIi+! by the pattern/color decoder 50. It can be converted into eB axis color signal and luminance signal. These color signals and luminance signals are converted into analog signals by the output interface circuit 51 and supplied to a picture tube (not shown). Then, image information such as character information signals is displayed on this picture tube.

Next, the characteristic operation of the present invention will be explained.The video signal clamped to a predetermined DC potential by the clamp circuit 22 is supplied to one input terminal of the comparator 25, and is also supplied to the switch 11-circuit 26. . This video signal is shown in Figure 4(a).
Shown below. The switch circuit 26Fi and the switch pulse P6 outputted from the AND circuit 37 are turned on only during the horizontal scanning period in which the character information signal is superimposed and the clock run-in signal CR is superimposed. This switch pulse P6 is shown in FIG. 4 (6). In this way, the clock run-in signal CR that has passed through the switch circuit 26 is supplied to the filter 27, and its average value is detected. Impedance conversion circuit 28 has a high input impedance. Therefore, filter 2
The DC voltage output from 7 is supplied to the other input terminal of the comparator 25 while the DC level is maintained as it is. The output of the filter 27 is shown in FIG. 4(c). FIG. 5 is a circuit diagram showing an example of a specific configuration of the impedance conversion circuit 28. The impedance conversion circuit 28 is an amplifier circuit with a voltage follow configuration using an operational amplifier so that the DC voltage obtained from the arrow filter 27 is supplied as a slice voltage to the comparator 25 while maintaining the DC level. It has become. In this way, by detecting the average value of the clock run-in signal CR and setting the slice level of the text information signal, it is possible to always obtain the optimum slice level even if the amplitude of the text information signal changes. I can do it. FIG. 4(d) shows the character information signal separated by the comparator 25.

Here, the operation of the portion that outputs the switch pulse P6 will be explained. As mentioned above, the bit counter 35 receives the horizontal synchronization signal HD output from the synchronization separation circuit 35 (Fig. 6(a)
)), and the sample pulse SP
According to the count output of the bit counter 35, the decoder 36 generates a pulse Pa (see FIG. 6(b)) having a phase and a pulse width that match the superimposition area of the clock run-in signal CR that is added to one horizontal scanning period. Outputs every horizontal scanning period.

The pulse Ps is output from the AND circuit 37 as a switch pulse P6 only during the horizontal scanning period when the character information signal exists. This is because if the switch pulse Pa is output during a horizontal scanning period other than the horizontal scanning period in which the character information signal is superimposed, an incorrect slice level will be obtained. The operation for detecting a horizontal scanning period in which a character information signal exists is as follows.When a character information signal is superimposed on any horizontal scanning period from IOHth to 21H of the vertical blanking period, the CPU 4 J first connects the output line (a) of Ilo boat 40 through the data bus.
is set to the level, and (b) to (1) are set to the 0 level. This entire operation is shown as step S in FIG. This l, C
PU4 is written R as shown in step S of FIG.
AM, 9;? Clear. The shift register 39 is controlled by the load pulse P4 from the decoder 38.
Parallel data from port 40 is read and shifted using horizontal synchronization signal HD as a clock input. The load pulse P4 is shown in FIG. 6(c). Load pulse P4 is IO
It is set to low level by the H-th horizontal synchronization signal HD, and 1
The parallel data of the Ilo circuit 40 is transferred to the shift register 39 at the falling timing of the pulse 2 of the angular polarity that is set to high level by the 1H horizontal synchronization signal HDK.
loaded into. As a result, the output IAKd of the shift register J6, as shown in FIG. 6(d), provides a pulse pH whose phase and width match those of the KIOH-th horizontal scanning period. As shown in FIG. 6(e), the AND circuit 37 opens its gate in response to the pulse P, and allows the pulse Ps to pass through as the pulse P6. This pulse P6 closes the switch 26, and the comparator 25 performs a slicing operation on the character information signal according to the DC voltage from the filter 27. Now, if a character information signal exists during this IOH-th horizontal scanning period as shown in FIG. .9 will be incorporated. After this, the CPU 41 determines whether or not the data of the character information signal has been loaded into the loading RAM 33 (step S3). If the data has been loaded in the 15-th manner as it is now, the character information is stored in the 10th horizontal scanning period. The existence of the signal is stored in the calculation RAM 43. This operation is shown as step 4 in FIG. After this,
The CPU 41 sets the output line of the Ilo circuit 40 to the level, sets the output lines a and e to 0 to the 0 level, and detects whether or not a character information signal exists during the 12H horizontal scanning period. Thereafter, output lines (c) to (1) are set to the level one by one in the same way, and it is detected whether or not the character erasure @ sign exists in each horizontal scanning period, and if it exists, the horizontal The scanning period is stored in the calculation RAM 43. This operation is shown in Fig. 7 in 2 steps S,,S.

When the detection operation up to the 021H horizontal scanning period is completed, the CPU 1f converts only the output line of the I/O circuit 40 corresponding to the horizontal scanning period stored in the calculation RAM 4.9 into a level. Set. This operation is shown in step 718 in Figure 7. For example, 16H and 21H.
If the character information signal is heavy during the H-th horizontal scanning period, the output lines (g) and (1) are set to level 16-.

In this way, when the detection of the horizontal scanning period in which the character information signal exists is completed and the period is set in the I/CI board 40, only the period set in the I10 circuit 40 is detected from the next field. Pulse P from shift register 39,
During this period, the pulse P8 passes through the AND circuit 37 and the switch pulse P6 is output to the switch 26.
The switch 26 is turned on.

As a result, during the horizontal scanning period of 9.16H and 21H, the filter 27 obtains a DC voltage that adjusts to the average value of the cycle-in signal CR, and the comparator 25 uses the DC voltage as a slice level to obtain a character. Information signals are separated.

As explained above, according to this embodiment, the average value of the clock run-in signal of the text information signal is calculated, and this average value is used as the slice level to separate the text information signal from the video signal. The optimum slice level can always be automatically obtained even if the amplitude of the text information signal changes. Furthermore, since the average value detection operation is performed only during the horizontal scanning period when a character information signal is present, the average value obtained from the filter 27 does not fluctuate unintentionally. The character information @ number can be separated at the slice level.

[Efficacy of invention]

As described above, the present invention provides an automatic slicing circuit that can always automatically set an optimal slice level even when the amplitude of the text information signal changes and separate the text information signal from the video signal. can do.

[Brief explanation of the drawing]

Fig. 1 is an N1 path diagram showing a conventional slice circuit, Fig. 2 is a signal waveform diagram for explaining the operation of Fig. 1, Fig. 3 is a circuit diagram showing an embodiment of the present invention, Fig. 4 is a signal waveform diagram for explaining the operation of FIG. 3, FIG. 5 is a circuit diagram showing an example of the filter in FIG. 3, and FIG. 6 is a signal waveform diagram for explaining the operation of FIG. 3. FIG. 7 is a flowchart for explaining the operation of FIG. 3. 22... Clamp circuit, 23... Oscillation circuit, 24...
...Synchronization separation circuit, 25...Comparator, 26...
・Switch circuit, 27...Filter, 28...Inbit 1-7 bus conversion circuit, 29...'Y Nbling pulse generation circuit, 34...Line link, 35...Bit counter, 36.38...decoder, 37...
AND circuit, 39...shift register, 40...I
10 ports, 41... CPU, 42... Arithmetic RAM
.

Claims (1)

[Claims] clamping means for clamping a video signal on which a text information signal is superimposed to a predetermined DC potential; horizontal scanning period detection means for detecting a horizontal scanning period on which the text information signal is superimposed; The clock run-in signal is extracted according to the video signal by turning on the clock run-in signal during a horizontal scanning period in which a video signal is inputted and detected by the detection means and the clock run-in signal is at 1 tatami. a switch means, an average value detection means for detecting the average value of the clock run-in signal extracted by the switch means, and a video output from the clamp means using the average value detected by the average value detection means as a slice level. and slicing means for separating a character information signal from a signal.