JPS5910261A - Semiconductor logical circuit device - Google Patents

Abstract

PURPOSE:To largely reduce the write time of an ROM by enabling the write of contents in the ROM device by the addition of the process of injecting the same conductivity type impurity as source and drain regions. CONSTITUTION:The part of a gate insulation layer 181 is implanted the same conductivity type impurity as that of source region 15 and drain region 16, i.e., P type impurity, and the surface of an Si substrate 11 is doped with the P type impurity, resulting in the formation of P<+> type impurity regions, i.e., the first impurity regions 24 and 25 respectively. Since these regions 24 and 25 work as a part of the source region 15 and drain region 16, an actual working IGFET is constituted. On the other hand, the part of a gate insulation layer 182 is implanted the reverse conductivity type impurity to that of the source region 15 and drain region 16, i.e., N type impurity, and the surface of the Si substrate 11 is doped with the N type impurity, resulting in the formation of N type impurity regions, i.e., the second impurity regions 26 and 27 respectively. Since these regions 26 and 27 have N conductivity type which is reverse to that of the source region 15 and drain regions 16, only non working IGFET is constituted.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to improvements in semiconductor logic circuit devices.

[Technical background of the invention and its problems] The development of semiconductor memories has progressed rapidly in recent years, and among them, random access memory (Random ac
The increase in capacity and speed of cess memory (RAM) is remarkable. At the same time, read-only memory (Read-only memory)
Demand for ROM (abbreviated as ROM) has also increased considerably in certain fields. There are various applications in this field, such as code conversion, adding functionality to calculators, and peripherals for computers. It is necessary to develop ROMs with specific contents according to these uses, and each has the disadvantage of not being compatible.

If we consider this matter of developing 9 R and OM according to the determined use as 1) writing the contents to LOM, R
Compared to AM, ROM requires an enormous amount of writing time. However, in other words, it has an advantage that RAM does not have, in that the contents once written are retained semi-permanently regardless of the power supply or the like. Therefore, in order to take advantage of the above-mentioned advantages, it is important to shorten the above-mentioned writing time as much as possible.

There are roughly two types of writing means currently in use. That is, the first method is to write into a completed ROM chip using electrical means, and the second method is to write during the ROM chip manufacturing process. In the first method, it is also possible to erase the written contents, which is very advantageous because the contents of the ROM can be determined while considering the system before it is completed. On the other hand, however, it requires a dedicated device for writing and erasing, and it is necessary to write data one by one, so the lack of mass productivity is economically disadvantageous. On the other hand, in the second method, writing time is long and erasing is impossible, but when creating a ROM with once-determined contents, a large amount can be written at one time, so it has the advantage of being mass-producible. Furthermore, this second method performs writing by changing the photolithographic mask (hereinafter referred to as mask) used during the manufacturing process, so it is generally called a mask ROM, but it is not possible to change the mask at any stage of the process. The time required to complete the desired ROM varies considerably depending on whether the ROM is written or not. Therefore, when creating a mask ROM, it is important to determine which process mask should be used for writing in order to shorten the period of time required to complete a ROM having arbitrary contents.

Next is the insulated gate field effect transistor (hereinafter referred to as IGFET).
We will explain the conventional method for creating a mask ROM using the P-channel I
The first step is to explain the basic manufacturing process of integrated circuits using only GFETs.
This will be briefly explained using figures.

That is, FIG. 1(a) shows a diffusion process in which an n-type silicon substrate α
Diffusion apertures (as, C14) are provided at desired positions of the silicon oxide film (12+) provided on the main surface of D, respectively, and P-type impurities are doped into the substrate through the apertures (03) and (14). Paired source region (I5) and drain region 0
form υ.

FIG. 2B shows an oxidation step in which a silicon oxide film (+21) is formed on the surfaces of the source region o5) and drain region aO.

FIG. 2C shows a step of forming a hole for gate oxidation, in which the silicon oxide film α between the source region 051 and the drain region (16) is removed, and an opening 0η for gate oxidation is formed. FIG. 1D shows a gate oxidation step in which a gate oxide film, that is, an insulating layer 081, is formed on the surface of the silicon substrate 01) exposed through the opening aη. FIG. 5(e) shows the process of making holes for contacts, and the source region 05 and the drain region 06 are shown in FIG.
) is removed, and openings 0 and Qσ for contact are respectively formed. In the same figure (0 is a conductive film forming step, a source region 09 and a drain region (lfil) exposed from the opening are respectively provided with a source conductive layer Qυ and a drain conductive t i az , and a gate insulating layer (+81
A gate conductive layer (c) is formed on top to complete the process.

Now, when forming a mask ROM, in general, in the process shown in FIG.
So, as a process that can selectively form a necessary IGFET (hereinafter referred to as an actual GFET) and an unknowable IGFET (hereinafter referred to as an immobile IGFET), the steps are (a),
Examples include steps (c) and (f). Figures 2, 4, and 6 are planar pattern diagrams of the main parts of the mask ROM in which the mask was changed in the steps (a), (C), and (f), respectively, and writing was performed according to the ffN pattern. , FIG. 3(a), FIG. 5(a) and FIG. 7(a) are sectional views taken along line A-A' in FIGS. b), FIG. 5(b) and FIG. 7(b) are
FIG. 6 is a sectional view taken along line BB' in FIGS. 2, 4, and 6, respectively. In these figures, 0 is the silicon oxide film, Q51 is the source region, ae is the drain region, α811
．． α is a gate line edge layer, ■υ is a source conductive layer, (2) is a drain conductive layer, (c) 1.C23) 2 is a gate conductive layer.

For example, when writing by changing the mask in the step of FIG. 1(a), as shown in FIGS. 2 and 3(b), the protrusion α51a at the end of the source region α where you want to configure an immobile IGFET is On the other hand, as soon as the actual IGFET is configured as shown in FIGS. 2 and 3(a), the mask is changed so that the protrusion 05) a of the source region Q51 remains as it is, and the opening for source diffusion is removed. A hole (13) is provided and a source region 0 is formed. However, in this case, since it is located at the beginning of all the steps, the writing time up to the step shown in FIG. 1(f) becomes eight times longer until the ROM is completed.

In addition, when writing is performed by changing the mask in the process of FIG. 1(C), the fixed IG as shown in FIGS.
The location where you want to configure the FET is the opening 07 for gate oxidation.
As shown in FIGS. 4 and 5(a), an opening 07 for gate oxidation is provided at the location where the actual IGFET is to be constructed.
) 1, but this does not mean that the transistor is completely removed, just because the threshold voltage of the immobile IGFBT increases to a certain extent. Therefore, leakage current becomes a problem depending on the usage conditions.

On the other hand, when writing is performed by changing the mask in FIG. 1 (0 step), as shown in FIG. 6 and FIG.
6 and 7 (a
), the mask will be changed to leave the gate conductive layer (c) on the gate insulating layer (1811) where you want to configure the actual IGFET. ) Since the time required after the process is sufficient (→,
(C) It has the advantage of being extremely short compared to writing in the process, but the leakage current that occurs between the source and drain regions becomes a problem if no measures are taken in the region that should originally become a channel. becomes.

[Object of the Invention] The present invention provides a novel semiconductor logic circuit device that eliminates the above-mentioned drawbacks, and in particular, provides a novel semiconductor logic circuit device that does not impair the characteristics of semiconductor elements formed on a semiconductor substrate and greatly reduces the writing time of ROM. It is an attempt to shorten it.

[Summary of the Invention] That is, strip-shaped source and drain regions are formed parallel to each other on the surface of a semiconductor substrate, source and drain conductive layers are respectively formed in the source and drain regions, and the source and drain regions between the source and drain regions are formed. A gate insulating layer is formed on a selected semiconductor substrate surface, and a gate conductive layer is provided on the gate insulating layer so as to expose the gate insulating layer between at least one of the source and drain regions. Then, in order to configure an actual IGFET, impurities of the same conductivity type as the source and drain regions are implanted into the surface of the semiconductor substrate directly below through the exposed portion of the gate insulating layer in the selected one of the gate insulating layers, and An impurity region of the same conductivity type is formed, the other end of which is connected to a region forming a gap with the gate conductive layer, and whose other end extends to below the end of the gate conductive layer, and the impurity region is made part of the source or drain region. Configure IGFET.

In this way, by adding the step of implanting impurities of the same conductivity type as the source and drain regions, it becomes possible to write the contents of the ROM device, and it is possible to manufacture the device up to the step shown in FIG. 1(f) regardless of the contents of the ROM. It became.

[Embodiments of the Invention] Next, the present invention will be explained in detail with reference to an embodiment shown in FIG. First, various processes are applied to the n-type semiconductor silicon substrate, which is basically the same as the process shown in FIG. 1 except for some steps.
The same process will be explained using FIG.

First, as shown in FIG. 1(a), an n-type silicon substrate 0υ
After depositing a silicon oxide film 07J on the main surface of the film, a plurality of substantially parallel diffusion holes spaced apart from each other are formed at desired positions on this film by ordinary photolithography (hereinafter referred to as PEP).
13) and (14) are provided to expose the silicon substrate 01). Next, a P-type impurity is doped into the substrate from this opening 0:q) and H to form a P-type region, that is, a source region (15
1 and a drain region (16) are formed. As shown in FIGS. 8 and 9, the source region Q51 and drain region Oe form substantially parallel stripes spaced apart from each other.

Next, as shown in FIG. 1(b), the source region 05)
Then, a silicon oxide film α2 is formed on the surface of the drain region (16) by a normal oxidation method.

Thereafter, as shown in FIG. 1(C), the silicon oxide film a between the selected source region α9 and drain region (16) is removed by the PEP method, and an opening 0 for gate oxidation is formed.
η5. form aη2. This opening 07)1. <1η2
As shown in FIGS. 8 and 9, the source and drain regions 051. Selected silicon substrate 0 between α0
1) and the region (151, (1(i)) is formed so that a part of the surface is exposed.

Next, as shown in FIG. 1(d), FIG. 8, and FIG. 9, a gate is formed on the surface of the silicon substrate 01) exposed through each of the openings 07), An oxide film, that is, an insulating layer (18+, 2, Os2) is formed, respectively.

After that, as shown in FIG. 1(e) and FIG.
Contact holes H and +2 are formed in the silicon oxide film on the source region 09 and the drain region aω by the method.
01 is formed.

Next, as shown in FIG. 1(f), FIG. 8, and FIG. layer (forming two layers, and further forming a gate insulating layer Q81.
．． (A gate conductive layer C23, , 2 is formed on the gate conductive layer C23, , (23). As shown in FIGS. 8 and 9, for example, a gate insulating layer (1
@1.08) At the position adjacent to 2, the source (*r
It is provided so as to intersect with the i region (1:) and the drain region (+61), and between the source region (15) and the drain region (Hil), a part of it is provided along each gate insulating layer along the source/drain region. The gate conductive layer (c) 1 extends across the gate conductive layer s tQ''2.
．． (C) The extended portion of 2 is here a gate insulating layer dl19 between the source region and the drain region aO, respectively.
A gap is provided to form an exposed portion of 1.0192 mm. This gate insulating layer 081. , it is not always necessary to provide the exposed portions of the QIC2 symmetrically as shown.

Next, an actual IGFET and a low-current IGFET are selected and formed according to the desired information pattern. For example, the 8th
Assuming that the active IGFET is configured in the gate insulating layer 0811 portion and the lower current IGFET is configured in the gate insulating layer 0812 portion as shown in FIGS. 8 and 9, FIGS. As shown in (a), the working IG
Final gate insulating layer Q81 configuring the FBT. An impurity of the same conductivity type as that of the source region (15) and the drain region θω, that is, a P-type impurity, is irradiated to the portion of the gate insulating layer (181, 181) by, for example, a normal ion implantation method.

P-type impurities are doped into the surface of the silicon substrate 011 immediately below through the exposed portion of the p-1-By impurity region, that is, the first
Impurity regions Q4) and 122 are formed, respectively. That is, as shown in FIG. 9(a), the first impurity region Q(
In (a) and (c), one end is connected to the source region 0!19 and the drain region, respectively, and the other end extends directly below the side end of the extension of the gate conductive layer 0th floor. Since these regions @ and (c) act as part of the source region (15) and drain region 0υ, the source region 05)
, CI! 4) , drain region QB) , C2
An actual IGFET is constructed with a gate insulating layer 0811 and a gate conductive layer Q3)1.

On the other hand, impurities of the opposite conductivity type to the gate insulating layer (1g+2 part, source region Q51 and drain region 06), that is, n-type impurity, are irradiated to the surface of the silicon substrate 01) immediately below through the exposed part of the gate insulating layer 082. The n-type impurity region, that is, the second impurity region (26
') and (27) are formed, respectively. That is, Fig. 9 (
As shown in b), the second impurity region (c), (two regions) has one end connected to the source region (15) and drain region aω
and the other ends extend below the side end portion 1u of the extended portion of the gate conductive layer QJ2. However, this area (c)
(Since 2n is of the n conductivity type opposite to the source region Q51 and drain region 061, the source region (15) 1
It has a structure as an IGFET with the drain region α6), the gate insulating layer 0812, and the gate conductive layer (c) 2, but the drain region (16) and the gate conductive layer (c)
In the region of the opposite conductivity type from the side end of the extension part of 2, an actual IGFET is not configured, but is simply a lower current IGFET.
It merely configures an FET.

[Effect of the invention] Consider the characteristics of the ROM device 4 having such a structure.

As mentioned above, the impurity having the same conductivity type as the channel to be formed is doped at a high concentration between both the source region, the drain region, and the gate conductive layer of the IGFBT. The series resistance component between the conductive layers can also be almost ignored.

Furthermore, when doping by ion implantation, there is no need for particularly high-width processing, so Ae can be used as the metal for the conductive layer as before, and the gate conductive layer, source region, and drain region can be self-aligned. Besides, the time required to dope is short.

In addition, where an IGFET is required, a P-channel IGFET is installed.
P-type impurity in T, n-channel GFET
All that is required is to dope a type impurity to create an impurity region that functions as a source region or a drain region, and by adding this step, it becomes possible to write the contents of the ROM device. It has many advantages such as being able to be manufactured regardless of the content.

On the other hand, if a metal that is stable even at the temperature required for diffusion is used as the metal of the conductive layer, then the first problem. The second impurity region may be formed by normal diffusion.

By the way, in the above embodiment, an n-type impurity is doped for a P-channel IGFET, and a P-type impurity for an n-channel IGFET is doped directly under the exposed gate insulating film in a place where the IGFET is not required, and the threshold voltage is set by tL[. Although the transistor is made to have a high voltage so that it cannot function sufficiently as a transistor within the power supply voltage used, it goes without saying that such impurity doping is not necessary.

Further, in the above embodiment, a ROM writing method using a P channel was shown, but it is naturally applicable to an I'LOM using an n channel or a CMO840M that combines both.

[Brief explanation of the drawing]

1(a) to (f) are process sectional views showing the basic manufacturing process of a conventional semiconductor logic circuit device, FIG. 2 is a planar pattern diagram showing an example of a conventional semiconductor logic circuit device, and FIG. 3 (
a) and (b) are lines A-A' and B in Fig. 2, respectively.
4 is a planar pattern diagram showing another example of a conventional semiconductor logic circuit device, and FIGS. 5(a) and 5(b) are respectively taken along line A-A' in FIG. 4. and B-B'
6 is a planar pattern diagram showing still another example of a conventional semiconductor logic circuit device, and FIG. 7(a) and (
b) is a sectional view taken along line A-A' and line B-B' in FIG. 6, FIG. 8 is a planar pattern diagram showing an embodiment of the semiconductor logic circuit device according to the present invention, and FIG. Figure (a
) and (b) are cross-sectional views taken along line A-A' and line B-B', respectively. 1]...Semiconductor substrate, 12...Silicon oxide film, 1
5... Source region, 16... Drain region, 170
, 17□ ... Opening for gate oxidation, 18, . 18°...Gate insulating layer, 19, λ)-opening for contact, 21...Source conductivity 1m, 22...Drain conductive layer, 2'31. '232 ・Gate conductive layer, 25
...First impurity region, Ah, 2'7...Second impurity region. zu 1 figure/f Ib lower 2 figure 3 mouth (ku) Cb)nt
/gz army 4-ku te figure (λ) (b) zu 6 figure'f7 figure

Claims (1)

[Claims] source and drain regions formed at a distance from each other on the main surface of the semiconductor substrate; source and drain conductive layers connected to the source and drain regions, respectively;
A gate insulating layer is provided between a gate insulating layer formed on the surface of the semiconductor substrate selected between the drain regions and at least one of the source and drain regions provided on the gate insulating layer. A gate conductor forming a gap such that the gate conductor Nli, provided on the surface of the semiconductor substrate directly below it,
A semiconductor logic circuit comprising an impurity region having the same conductivity type as a source and drain region, one end of which is connected to a region forming a gap with the gate conductive layer, and the other end extends to below one end of the gate conductor 1tl. Device.