JPS59101858A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS59101858A
JPS59101858A JP57212351A JP21235182A JPS59101858A JP S59101858 A JPS59101858 A JP S59101858A JP 57212351 A JP57212351 A JP 57212351A JP 21235182 A JP21235182 A JP 21235182A JP S59101858 A JPS59101858 A JP S59101858A
Authority
JP
Japan
Prior art keywords
substrate
electronic components
electronic component
electronic
lsi chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57212351A
Other languages
Japanese (ja)
Inventor
Tetsuo Hayashi
哲夫 林
Masatoshi Osato
大里　雅敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57212351A priority Critical patent/JPS59101858A/en
Publication of JPS59101858A publication Critical patent/JPS59101858A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To attain the improvement of reliability of connection between each electronic component at low cost by a method wherein a circuit is composed of the first substrate whereon a plurality of electronic components are mounted, the second substrate wherein a hole is formed at the position corresponding to each electronic component and which is joined to the first substrate, filler, and a conductor film formed to connect each electronic component. CONSTITUTION:The second substrate 7 having shape dimensions slightly larger than those of a plurality of the electronic components 1, having windows at the positions corresponding to that of the electronic components 1 mounted on the first substrate 3, and having a height nearly equal to that of the electronic component 1 is joined to the first substrate 3 whereon the electronic components 1 such as an LSI chip, etc. are mounted. The clearances between the electronic components 1 and the windows of the second substrate 7 are filled with heat resistant resin 8, etc., and accordingly assembly is so performed that the surface of the electronic component 1 and that of the second substrate 7 become on the same plane which is smooth. The conductor pattern 9 which electrically connects each electronic component 1 is the one formed of a thin film of aluminum or gold, etc. formed over the entire plane by a method such as evaporation or thick film printing into a desired pattern by photolithography technique.

Description

【発明の詳細な説明】 本発明はハイブリッドＩＣ（集積回路）に関し、特に、
高信頼度を有し高密度実装が可能なリードレスハイブリ
ッドＩＣに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid IC (integrated circuit), and in particular,
The present invention relates to a leadless hybrid IC that has high reliability and can be mounted at high density.

従来のハイブリッドＩＣにおいては、厚膜または薄膜か
らなる回路パターンが予め形成された基板上に複数個の
ＬＳＩ（大規模集積回路）等の電子部品が塔載され、こ
れらの電子部品は半田付あるいはワイヤボンディング等
により前記基板上の回路パターンと電気的に接続され、
これにより、前記電子部品間の相互配線が行なわれてい
る。このような半田付あるいはワイヤボンディング等に
より機械的に接続されている接続点においては故障発生
の確率が高い。高信頼度ハイブリッドＩＣを実現するた
めにはボンディングワイヤを用いない他の接続手段が採
用されている。例えば、電子部品がＬＳＩチップである
場合には、ＬＳＩチップ内のポンディングパッドにＬＳ
Ｉチップ製造時に予めビームリードを設けｆｃＪあるい
は該ポンディングパッド上にクロムや銅の薄膜を形成し
、この上に半田バンクを設けることによフボンディング
ワイヤを使用せずに接続する手段がある。In conventional hybrid ICs, electronic components such as multiple LSIs (Large Scale Integrated Circuits) are mounted on a substrate on which a circuit pattern made of thick or thin film is formed in advance, and these electronic components are soldered or bonded. electrically connected to the circuit pattern on the board by wire bonding or the like;
Thereby, mutual wiring between the electronic components is performed. There is a high probability of failure occurring at connection points that are mechanically connected by soldering, wire bonding, or the like. Other connection means that do not use bonding wires have been adopted to realize highly reliable hybrid ICs. For example, if the electronic component is an LSI chip, the LS is placed on the bonding pad within the LSI chip.
There is a method of connecting without using bonding wires by providing a beam lead in advance during I-chip manufacturing, forming a thin film of chromium or copper on the fcJ or the bonding pad, and providing a solder bank thereon.

しかし、これらの接続手段では、ＬＳＩチップを製造す
る工程が複雑となシ、該ＬＳＩチップの価格が非常に高
くなるだけでなく、ＬＳＩチップはその表面を下方に向
けたフェイスダウンで基板に取り付けられるため、接続
点やＬＳＩチップの表面状態の外観目視チェックが不可
能となり、また、ＬＳＩチップ裏面が基板に接合されて
いないためＬＳＩチップからの熱の放散性が悪く、その
信頼性が悪いという欠点を有する。However, these connection methods not only complicate the process of manufacturing the LSI chip and make the LSI chip extremely expensive, but also require the LSI chip to be mounted face down on the board with its surface facing downward. This makes it impossible to visually check the external appearance of the connection points and the surface condition of the LSI chip, and because the back surface of the LSI chip is not bonded to the substrate, heat dissipation from the LSI chip is poor, resulting in poor reliability. It has its drawbacks.

第１図は従来のボンディングワイヤにより接続されたハ
イブリッドＩＣの断面図を示す。ＬＳＩチップ１と基板
３上の導体パターン２とはボンディングワイヤ４を介し
て接続されている。この接続手段はボンディングワイヤ
の接続点が多いため、この接続点における故障発生の確
率が高い。FIG. 1 shows a cross-sectional view of a hybrid IC connected by conventional bonding wires. The LSI chip 1 and the conductor pattern 2 on the substrate 3 are connected via bonding wires 4. Since this connection means has many bonding wire connection points, there is a high probability that a failure will occur at these connection points.

第２図はポンディングパッド上に半田バンプ５が設けら
れたＬＳＩチップｌを基板３上に形成された導体パター
ン２と半田付した状態を示す断面図である。FIG. 2 is a sectional view showing a state in which an LSI chip 1 having solder bumps 5 provided on bonding pads is soldered to a conductor pattern 2 formed on a substrate 3.

第３図はビームリード６を有するＬＳＩチップｌのボン
ディング状態を示す断面図である。ＬＳＩチップ１のポ
ンディングパッド部にビームリード６が形成されており
、該ビームリード６は基板３上の導体パターン２にボン
ディングされている。FIG. 3 is a cross-sectional view showing the bonding state of an LSI chip 1 having beam leads 6. As shown in FIG. A beam lead 6 is formed at a bonding pad portion of the LSI chip 1, and the beam lead 6 is bonded to a conductor pattern 2 on a substrate 3.

第２図および第３図に示したいずれの接続手段もＬＳＩ
チップ製造工程が複雑になりその製造コストが高くなる
。また、ＬＳＩチップ表面が基板と直接接合されていな
いためＬＳＩチップからの熱の放散性が悪く、高信頼度
を必要とする高消費電力のハイブリッドＩＣには不向き
である。Both connection means shown in Fig. 2 and Fig. 3 are LSI
The chip manufacturing process becomes complicated and the manufacturing cost increases. Furthermore, since the surface of the LSI chip is not directly bonded to the substrate, heat dissipation from the LSI chip is poor, making it unsuitable for high power consumption hybrid ICs that require high reliability.

本発明の目的は上述の欠点を除去しボンディングワイヤ
や半田付けによる接続を使用しないハイブリッドＩＣを
提供することにある。The object of the present invention is to eliminate the above-mentioned drawbacks and to provide a hybrid IC that does not use bonding wires or soldered connections.

本発明のハイブリッドＩＣは、複数の電子部品が取り付
けられた第１の基板と、該第１の基板上の前記各電子部
品と対応する位置にそれぞれ穴が形成され該第１の基板
と基板面相互が接合された第２の基板と、前記各電子部
品と前記各穴との間隙に充填された耐熱性樹脂等の充填
材と、前記第２の基板の表面に前記各電子部品間の接続
を行なうために形成された導体膜とから構成されている
。The hybrid IC of the present invention includes a first substrate to which a plurality of electronic components are attached, and a hole is formed at a position corresponding to each of the electronic components on the first substrate, and the first substrate and the substrate surface are connected to each other. A second substrate that is bonded to each other, a filler such as a heat-resistant resin filled in the gaps between the electronic components and the holes, and a connection between the electronic components on the surface of the second substrate. and a conductor film formed to perform the following.

次に本発明について図面を参照して詳細に説明する。Next, the present invention will be explained in detail with reference to the drawings.

第４図は本発明の一実施例を示す断面図である。FIG. 4 is a sectional view showing an embodiment of the present invention.

本実施例において、第１の基板３にはＬＳＩチップ等の
複数の電子部品１を搭載している。該第１の基板３には
、さらに、該電子部品１の形状寸法よ多やや大きい形状
寸法を有し、かつ、第１の基板３に搭載された電子部品
１の位置と対応する位置に窓を有し、また、電子部品１
の高さとほぼ等しい高さを有する第２の基板７が接合さ
れている。In this embodiment, a plurality of electronic components 1 such as LSI chips are mounted on the first substrate 3. The first board 3 further has a window having a shape and size slightly larger than the electronic component 1 and at a position corresponding to the position of the electronic component 1 mounted on the first board 3. and also has an electronic component 1
A second substrate 7 having a height approximately equal to that of is bonded.

このように、電子部品１は第２の基板７に設けられた窓
の内側に配置される。また、前記電子部品ｌと第２の基
板７の窓との間隙には、耐熱性樹脂８等が充填され、前
記電子部品１の表面と第２の基板７の表面とが平滑な同
一平面となるよう組み立てられる。In this way, the electronic component 1 is placed inside the window provided in the second substrate 7. Further, the gap between the electronic component 1 and the window of the second substrate 7 is filled with heat-resistant resin 8, etc., so that the surface of the electronic component 1 and the surface of the second substrate 7 are on the same smooth plane. It can be assembled as follows.

各電子部品１間を電気的に接続する導体ノ（ターン９は
、前記平滑となった平面全体に蒸着または厚膜印刷等の
方法で形成したアルミニウムｔたは金等の薄膜をフォト
リソグラフィー技術により所望のパターンに形成したも
のである。The conductor (turn 9) that electrically connects each electronic component 1 is a thin film of aluminum or gold formed by vapor deposition or thick film printing on the entire smooth plane using photolithography technology. It is formed into a desired pattern.

以上、本発明には、ボンデインディンクワイヤビームリ
ードおよび半田バンプ等を使用せずに各電子部品間の相
互配線を行なうことができるので各電子部品間の接続信
頼性の向上を達成でき、また電子部品に特殊なビームリ
ードや半田バンプ等を設ける必要が無いため低価格化を
達成できるという効果がある。さらに、電子部品が、Ｌ
ＳＩチップの場合には、その５接合は基板に対してチッ
プ全面で行なわれるためＬＳＩチップの発生する熱の放
散性が良いという効果もある。As described above, the present invention enables mutual wiring between electronic components without using bond-in-dink wire beam leads, solder bumps, etc., thereby improving connection reliability between electronic components. Since there is no need to provide special beam leads, solder bumps, etc. to electronic components, there is an effect that lower costs can be achieved. Furthermore, electronic components are
In the case of an SI chip, the 5-junction is performed on the entire surface of the chip with respect to the substrate, which has the effect of good dissipation of heat generated by the LSI chip.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はワイヤボンディングによ多接続を行なう従来の
ハイブリッドＩＣの断面図、第２図は半田バンプにより
接続を有力う従来のハイブリッドＩＣの断面図、第３図
はビームリードによ多接続を行なう従来のハイブリッド
ＩＣの断面図および第４図は本発明の一実施例を示す断
面図である。 図において、１・・・・・・ＬＳＩチップ、２・・・・
・・導体パターン、３・・・・・・第１の基板、４・・
・・・・ボンデイングワイヤ、５・・・・・・半田バン
プ、６・・・・・・ビームリード、７・・・・・・第２
の基板、８−・・・樹脂、９・・・・・・導体パターン
。Figure 1 is a cross-sectional view of a conventional hybrid IC in which multiple connections are made by wire bonding, Figure 2 is a cross-sectional view of a conventional hybrid IC in which multiple connections are made by solder bumps, and Figure 3 is a cross-sectional view of a conventional hybrid IC in which multiple connections are made by beam leads. A sectional view of a conventional hybrid IC and FIG. 4 are sectional views showing an embodiment of the present invention. In the figure, 1... LSI chip, 2...
...Conductor pattern, 3...First substrate, 4...
...Bonding wire, 5...Solder bump, 6...Beam lead, 7...Second
board, 8--resin, 9--conductor pattern.

Claims (1)

【特許請求の範囲】[Claims] 複数の電子部品が取シ付けられた第１の基板と、該第１
の基板上の前記各電子部品とに対応する位置にそれぞれ
穴が形成され該第１の基板と基板面で相互に接合した第
２の基板と、前記各電子部品と前記各穴との間隙に充填
された耐熱性樹脂等の充填材と、前記第２の基板の表面
に前記各電子部品間の接続を行なうために形成された導
体膜とから構成されたことを特徴とするハイブリッド集
積回路。a first board on which a plurality of electronic components are attached;
holes are formed at positions corresponding to each of the electronic components on the substrate, and a second substrate is bonded to the first substrate at the substrate surface, and a gap between each of the electronic components and each of the holes. A hybrid integrated circuit comprising a filler such as a heat-resistant resin, and a conductor film formed on the surface of the second substrate to connect the electronic components.
JP57212351A 1982-12-03 1982-12-03 Hybrid integrated circuit Pending JPS59101858A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57212351A JPS59101858A (en) 1982-12-03 1982-12-03 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57212351A JPS59101858A (en) 1982-12-03 1982-12-03 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS59101858A true JPS59101858A (en) 1984-06-12

Family

ID=16621098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57212351A Pending JPS59101858A (en) 1982-12-03 1982-12-03 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS59101858A (en)

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