JPS5910140B2 - Transmitting device for power line carrier communication equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power line carrier communication device that is optimal for sequentially sending commands from one location to a plurality of different locations using power wiring.

2. Description of the Related Art In recent years, due to the power crisis, the spread of various electrical devices, and the soaring cost of electricity, there is a growing demand among business entities to limit their power consumption to below a certain value. An effective method to meet this request is to detect the amount of electricity consumed at the power receiving end, constantly compare this value with a separately set limit value, and if the amount of electricity consumed exceeds the limit value, the electrical wiring in this premises It is a good idea to temporarily force off some of the electrical devices connected to the device. In this case, it becomes necessary to transmit a signal from the device that performs the size comparison to each electrical device connected to the wiring to turn it off when a predetermined condition is met.
In addition, it is often convenient to control various types of these devices independently and remotely. If power wiring is used as a signal line for transmitting these signals, construction of dedicated line facilities is not required even in existing buildings, which is extremely convenient. However, when power wiring is viewed as a signal line, as is well known, the noise level is extremely high, and the form of the transmission signal requires a simple method to prevent leakage to the outdoors. First, there is a need to reliably transmit signals independently to a large number of distributed electrical devices. The present invention
This was done to provide a power line carrier communication device suitable for these applications, and will be explained in detail below with reference to the drawings. FIG. 1 shows a main part configuration diagram of the present invention on a transmitting side incorporating the present invention.

In the figure, 1 is a signal input unit that determines which command signal is to be sent to the transmitting device of the present invention, and in normal cases, this corresponds to a signal generated by a processing device or a means such as when a human turns on a switch. . 2 is a corresponding command signal generation circuit 3-a to 3- that decodes the signal from the signal input section 1;
This is a decoding circuit for driving either one of n.

In this figure, the command signal generation circuit is shown as an example in which the transmitting section is configured by frequency division in which different frequencies are assigned to n different command signals, so that the signal is input from the input section 1. Then, by the operation of the decoding circuit 2, one of the command signal generating circuits 3-a to 3-n is driven for a certain period of time. 4-a to 4-n are amplifier circuits.

Reference numeral 5 denotes an 0R circuit which takes the 0R of the drive signals of the command signal generation circuits 3-a to 3-n.

Reference numeral 6 denotes a delay circuit, which delays the output from the 0R circuit 5 for a certain period of time and then generates a pulse.

7 is an address counter, and in an example in which command signals are transmitted independently to N receiving units, an N-ary counter is used.

8 indicates that this address counter has a predetermined content, for example, all B
It is a coincidence circuit that generates a pulse output of a constant width when a predetermined content such as it=0 is reached.

Reference numeral 9 is a set signal generation circuit to which a frequency different from that of the command signal generation circuits 3-a to 3-n is assigned, and 10 is an amplification circuit for this signal.

11 is an 0R circuit for command signals and reset signals, and 12 is a capacitor, which is provided to cut off the commercial voltage and inject the command signal and reset signal into the power line 13. Generally, the frequency of the above signals is The above function can be obtained by making the frequency much higher than the commercial frequency.

Reference numeral 14 denotes an amplification circuit for amplifying response signals (hereinafter referred to as answerback signals) from distributed receiving devices, which will be described later.

Reference numerals 15-a to 15-n are filter circuits that separate and receive answer back signals from a receiving device, and the figure shows an example in which the receiving device generates n types of answer back signals by frequency division.

Reference numeral 16 denotes a decoding circuit for the address counter 7, which generates an output to one of N circuits depending on the contents.

17-a to 11-n are AND gates for separating and detecting the answer back from the receiving device at address 1;
-a to 18-n indicate AND gates for separating and detecting the answer back from the receiving device at address 2. When there are N receiving devices, N sets of AND gates are required.

Therefore, 19 indicates the answer link output from the receiving device at address 1, and 20 indicates the answer link output from the receiving device at address 2.

A delay circuit 21 has a function of generating a control signal 4 in order to generate a pulse for a certain period of time after transmitting a command signal and wait for an answer back signal from the receiving device.
As described above, when one of the command signal generation circuits is driven for a certain period of time by the output of the decoder circuit 2, the corresponding output is sent to the power line 13 via the amplification circuit, the 0R circuit 11, and the capacitor 12. On the other hand, the output of the decoding circuit 2 is simultaneously inputted to the delay circuit 6 via the 0R circuit 5, and after the command signal transmission from the signal generation circuit is completed and the wait time for the answer back signal has elapsed, a pulse of a certain width is generated. The address counter 7 is incremented by 1. On the other hand, the receiving device that has received the command signal returns an answer pack by the operation described later, but after this signal is amplified by the amplification circuit 14, the contents of the answer pack are separated by filters 15-a to 15n. Received. On the other hand, the delay circuit 21
The output is generated for a certain period of time after the command signal is transmitted, and it is determined whether the received signal is an answer back signal for the command signal or not. Furthermore, by the operation of the decoding circuit 16, AND gates 17 and 18 separate and output which address the receiving device has received the answer packet from. That is, when the content of the address counter is 1, only the output lines input to the AND gates 17-a to 17-n of the decoder 16 become Hi, and the received answer back signal is output somewhere at the output terminal 19. . While performing such operations, when the address counter 7 reaches a predetermined value, the matching circuit 8 generates a pulse of a constant width, and drives the reset signal generating circuit 9 to send out a reset signal for a constant time.

Next, the operation of the receiving side, which receives the above transmission output and performs the intended operation, will be explained for the receiving device at address L.

In FIG. 2, 22 is a capacitor, which has exactly the same function as 12. 23-a to 23-n are filter circuits for selectively receiving signals generated by the command signal generation circuits 3-a to 3-n, and 24-a to 24-n are filter circuits 23-n, respectively. Circuits 25-a to 25-n that detect and amplify the outputs of -a to 23-n are amplifiers that convert these outputs into pulses.

26 is an 0R gate that outputs 0R from the amplifiers 25-a to 25-n.

This 0R gate output is input to delay circuits 30 and 31. The delay circuit 30 is a circuit that generates an output for a certain period of time after receiving the command signal and determines the timing for sending out the answer back signal. Reference numeral 31 denotes a circuit that generates a pulse after the end of the answer call, and causes an address counter 33, which has exactly the same configuration as the address counter 1 of the transmitting device, to count up by one.

On the other hand, 27 is a filter circuit for selectively receiving the output of the reset signal generating circuit 9, 28 is a detection amplification circuit, and 29 is an amplifier.

This output forces the contents of address counter 33 to be reset to the predetermined contents. That is, when a set signal is generated when the content of the address counter 7 of the transmitter is O, the address counter 33 of the receiver is also configured to be reset to O upon reception of this signal. 35 is a fixed address generation circuit which generates a signal corresponding to the address of the receiving device; in this figure, it generates a signal corresponding to address L.

34 is a matching circuit which generates a Hi output when the contents of the address counter 33 and the fixed address generation circuit 35 match, opens AND gates 36-a to 36-n, and separates and receives the received command signal. do.

37 is a signal output of a command signal from the transmitting side to the receiving side.

On the other hand, when the matching circuit 34 receives a command signal when it is Hi,
The AND gate 32 becomes Hi for a certain period of time, and the AND gates 39-a to 39-n are opened according to the receiving side status input 38, and one of the answer back signal generating circuits 40-a to 40-n is driven.

This answer back is used to allocate a signal indicating that it has been correctly received to the transmitted command signal, but this signal is sent to the 0R circuit 42 via amplifiers 41-a to 41-n. The signal is sent to the power line 13 by the power line 13. In this way, the command signal sent from the transmitting side is transmitted to all distributed N
The signal is received by the receiving side, passes through the 0R gate 26 and the delay circuit 31, and increments the address counter 33 by +1.

On the other hand, the selectively received command signal is AND gated by the output of the matching circuit 34, so only the receiving side where the contents of the address counter 33 match the fixed address will treat the received command signal as a valid command. This allows command signals to be sent from the transmitting side to each of the N receiving sides independently. On the other hand, since the address counter is incremented by +1 each time a command signal is received, the receiving side that can receive the command signal sequentially and generate the output will pass one by one, and in N times, all the receiving sides will receive the command sequentially. This makes it possible to transmit signals. On the other hand, it is obvious that the receiving side, which has effectively outputted the command signal, immediately sends a predetermined answer signal to the transmitting side through the answer-back signal generation circuit depending on the state. On the other hand, since synchronization between the sending and receiving sides is periodically maintained using a reset signal, it is natural that the address counter can be used to identify which receiving device the sending device that received the answer call came from. It is. FIG. 3 shows the above operation in a waveform diagram. In the same figure, A is the 0R output from the decoder circuit 2.
Show the output.

1 indicates a command signal and a reset signal output from the transmitting device, and corresponds to the output of the 0R circuit 11. C is the delay circuit 21
This output is the receive strobe signal for the answer back signal. 2 is the output of the delay circuit 6, which causes the address counter 7 to count up by +1. E shows the output of the matching circuit 8. is the output after the 0R gate of the command signal reception output on the receiving side, and is the output of the 0R gate 26. Figure is delay circuit 31
The address counter 33 is incremented by +1 with the output. H indicates the output of the matching circuit 34. 2 indicates the command signal output received at address L on the receiving side. Nu is the output of the AND gate 32 and is a command to send an answer back signal.
The answer back signal output from the receiver L is the output of the OR circuit 42. As described above, according to the present invention, the command signal itself is used as a timing signal in addition to the purpose of the command, and furthermore, by using a system in which the command signals are sequentially sent to the receiving device, special address It becomes possible to eliminate the trouble of transmitting codes, and it becomes possible to achieve the intended purpose with a simple communication circuit.

In the above embodiment, the command signal and the answer back signal are each frequency-divided, but it is clear that any signal form that can be separated by other methods may be used. Also, regarding the type of answer back signal, it is clear that only one type is sufficient if it is a confirmation signal to confirm whether or not an operation has been performed in response to a command signal.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of main parts of a transmitting device showing an embodiment of the present invention, FIG. This figure is a waveform diagram for explaining the operation of the apparatus shown in FIGS. 1 and 2. Note that the same symbols in the figures indicate the same parts, 1 is the signal input section,
2 is a decoding circuit, 3-a to 3-n are command signal generation circuits, 5 is an 0R circuit, 6 is a delay circuit, 7 is an address counter, 8 is a coincidence circuit, 9 is a set signal generation circuit, 11 is 0
R circuit, 15-a to 15-n are filter circuits, 16 is a decoding circuit, 17-a to 17-n are AND gates, 18
-a to 18-n are 1 gates, 21 is a delay circuit, 23-
a to 23-n are filter circuits, 26 is an 0R gate, 3
0 and 31 are delay circuits, 32 is an AND gate, 33 is an address counter, 34 is a coincidence circuit, 35 is a fixed address generation circuit, 36-a to 36-n are AND gates, 38 is a receiving side status input, 39- a to 39-n are AND gates,
40-a to 40-n are answer back signal generation circuits.

Claims (1)

[Claims] 1. In a transmitting device of a power line carrier communication device that transmits signals from one transmitting device to N distributed receiving devices, a command signal generation circuit of the number of types of commands to be transmitted, a reset signal generation circuit, and a command signal generation command are provided. means for transmitting a command signal for a certain period of time by driving a corresponding command signal generation circuit every time the command signal is transmitted; An N-address counter counts up by 1 each time a signal is transmitted, and when this N-address counter reaches a predetermined value, the reset signal generation circuit is driven each time, and a reset signal is sent for a certain period of time. A transmitting device for a power line carrier communication device, comprising means for transmitting.