JPS5910138B2 - Power line carrier communication system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power line carrier communication system that is optimal for sequentially sending commands from one location to a plurality of different locations using power wiring.

2. Description of the Related Art In recent years, due to the power crisis, the spread of various electrical devices, and the rise in electricity rates, there are increasing demands among business entities to limit power consumption within a certain value. An effective method to meet this request is to detect the amount of electricity consumed at the receiving end, constantly compare this value with a separately set limit value, and if the amount of electricity consumed exceeds the limit value, the amount of electricity consumed in this premises is It is a good idea to temporarily force off some of the electrical devices connected to the wiring. In this case, it becomes necessary for the device that performs the size comparison to transmit a signal to turn off the electric devices connected to the respective wirings under predetermined conditions. In addition, it is often convenient to control various types of these devices independently and remotely. If power wiring is used as a signal line for transmitting these signals, it is extremely convenient even in existing buildings since there is no need for dedicated line facilities. However, when looking at power wiring as a signal line, as is well known, the noise level is extremely high, and a simple method is required for the form of the transmission signal to eliminate external leakage from indoors to outdoors. However, there is also a demand for transmitting signals independently to a large number of distributed electrical devices.

The present invention was made to provide a carrier communication system most suitable for these applications, and will be explained in detail below with reference to the drawings. FIG. 1 shows a configuration diagram of main parts related to the present invention on a transmitting side incorporating the present invention.

In the figure, 1 is a part that inputs a signal that determines what kind of command signal is to be transmitted to the transmitting part of the present invention, and normally it is input by a processing device or by means such as turning on a switch by a human being. This shows the part where the generated signal is input to the main transmitter. 2 is a decoding circuit for decoding the signal from the signal input section 1 and driving one of the corresponding command signal generation circuits 3-a to 3-n.

In this figure, the command signal generation circuits 3-a to 3-n are
As shown in the example in which the transmitting section is configured by frequency division in which one frequency is assigned to n different command signals, when a signal is input from the signal input section 1, the decoding circuit 2 operates. Any one of command signal generating circuits 3-a to 3-n is driven for a certain period of time. 4-a to 4-n are amplifier circuits.

5 is 0R of the drive signal of the command signal generation circuits 3-a to 3-n.
This is an 0R circuit for taking the .

Reference numeral 6 denotes a delay circuit which delays the output of the 0R circuit 5 for a certain period of time and then generates a pulse.

7 is an address counter, and in an example in which command signals are transmitted independently to N receiving units, an N-ary counter is used.

8 indicates that this address counter 7 has a predetermined content, for example, all B
It is a coincidence circuit that generates a pulse output of one constant width when it has one content such as it=0.

Reference numeral 9 denotes a signal generation circuit which assigns a frequency different from that of the command signal generation circuits 3-a to 3-n and sets (Re8et) signal generation circuit;
is this amplification circuit.

11 is an 0R circuit for the command signal and reset signal; 12 is a capacitor provided to cut the commercial voltage and inject the command signal and reset signal into the power line 13; generally used for the above signal group. The above functions can be obtained because the frequency is much higher than the commercial frequency.

As described above, when one of the command signal generation circuits 3-a to 3-n is driven for a certain period of time by the output of the decoder circuit 2, the output is transmitted to the amplifying circuit and the 0R circuit 11, and the capacitor 1.
2 and sent out to the power line 13.

On the other hand, the output of the decoder circuit 2 is simultaneously inputted to the delay circuit 6 by the 0R circuit 5, and when the command signal generation circuit finishes sending out the command signal, the delay circuit 6 generates a pulse of a constant width, and the address counter 7 is increased by +1. Make the count up.

When the counter 7 reaches a predetermined value, the coincidence circuit 8 generates a pulse of a constant width, and the reset signal generation circuit 9
and sends out a reset signal on the power line 13. This situation is shown in a waveform diagram in FIG. In the same figure,
1 is an example in which the command signal generating circuit 3-1 is driven by the 0R output of the signal output from the decoder circuit 2. mouth is 0
This is the output signal of the R circuit 11 and is also a signal sent onto the power line 13 at the same time. C shows the output pulse of the delay circuit 6.
2 shows the output of the matching circuit 8. 5 shows an example of the output of the set signal generating circuit 9 which is sent out at this time. Next, the operation of the receiving side which receives the above transmission output and performs a predetermined operation will be explained with respect to the receiving section at address L. In FIG. 2, 14 is a capacitor which has exactly the same function as the capacitor 12. 15-a to 15-n are filter circuits for selectively receiving the signals generated by the command signal generating circuits 3-a to 3-n, and 16-a to 16-n are filter circuits 15-a to 15-n, respectively. A circuit 17 for detecting and amplifying the output of 15-n
-a to 17-n are the amplification amounts for pulsing this output.

21 is an 0R gate that sets the outputs of amplifiers 171 to 17-n to 0.
R.

The output of this 0R gate 21 is input to a delay circuit 22, which generates a pulse of a constant width after the output of the 0R gate 21 returns to LO, and causes the address counter 23 to count up by +1. This address counter has exactly the same configuration as the address counter 7 on the sending side. On the other hand, 18 is a filter circuit for selectively receiving the output of the reset signal generating circuit 9, 19 is a detection amplification circuit for this output, and 20 is an amplifier. Now, the output of this reset signal receiving circuit is input to the address counter 23, and when this signal is received, the contents of the address counter 23 are forcibly reset to a predetermined value. That is, if a set signal is generated when the content of the address counter 7 on the transmitting side is zero, the address counter 23 is also configured to be reset to zero upon receiving this signal. Reference numeral 25 denotes a fixed address generation circuit, which generates a signal corresponding to the address on the receiving side. In this figure, the fixed address generation circuit generates a signal corresponding to address L.

24 is a matching circuit, which generates a Hi output when the contents of the address counter 23 and the fixed address generation circuit 25 match, and this output is sent to AND gates 26-a to 26-.
It is connected as shown in the figure as one input of n.

The input to the other AND gate is the respective command signal reception output. And this AND gate 261a~
The outputs of 26-n are used as respective output terminals for command signals. That is, the command signal sent from the transmitting side is received by all the receiving sides, passes through the outputs of the 0R gate 21 and the delay circuit 22, and increments the address counter 23 by +1. On the other hand, the selectively received command signal is AND gated by the output of the matching circuit 24, so that only the receiving side whose address counter matches the fixed address will generate the received command signal as its output. On the other hand, each time a command signal is received, the address counter counts up by +1.
The receiving side, which sequentially receives and outputs command signals, has 1
Since the signals are shifted one by one, command signals are sequentially transmitted to all receiving sides. On the other hand, it will be clear from the above explanation that the address counters on the transmitting side and the receiving side are synchronized by the reset signal. This dynamic state on the receiving side is shown in a waveform diagram in FIG.

That is, the output from the 0R gate 21 is shown.

5 shows a waveform diagram showing the output of the delay circuit 22 along with correspondence to the contents of the address counter, and shows that the address counter shifts by one each time a command signal is received. 2 is the output of the coincidence circuit 24, which is shown on the receiving side of the address L in FIG. 2, and therefore generates a Hi output when the address counter has contents corresponding to the address L.
This is the output of the AND gate, and this figure shows an example in which the output is generated at 26-3. As described above, according to the present invention, the command signal is also used as the timing signal, and furthermore, the method of sequentially sending and receiving commands to the receiving side allows for many different variations as long as the number of bits of the address counter increases. The present invention provides an inexpensive communication method that is sufficiently stable in power line transport because it enables independent and sequential communication by simply sending a command signal and sending a single reset signal without assembling a code on the receiving side. provides the means to enable the implementation of a number of useful centralized control systems.

In this text, an example is shown in which a frequency is assigned to each command signal, but it goes without saying that any signal form that can be separated by other methods may also be used.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts showing an embodiment of the transmitting section of the present invention, FIG. 2 is a block diagram of main parts showing an embodiment of the receiving section of the present invention, and FIG. 3 is an explanatory diagram of the operation of the present invention. It is. In the figure, 3-a to 3-n are command signal generation circuits, 6 is a delay circuit, 7 is an address counter, 8 is a coincidence circuit, and 23
is an address counter, and 24 is a matching circuit.

Claims (1)

[Claims] 1. In a carrier communication system in which signals are transmitted from one device to N distributed reception sides using power lines, the transmission side has a number of command signal generation circuits corresponding to the types of transmission commands and the above-mentioned command signal generation circuits. a different reset signal generation circuit; an N-ary counter circuit that counts up by 1 each time the command signal is transmitted; and a N-ary counter circuit that counts up by 1 each time the command signal is transmitted; A transmitter is provided on the receiving side, and means for selectively receiving each of the transmission command signals and the reset signal transmitted from the transmitting side; An N-ary counter that is incremented by 1 based on the OR output of each receiving means of the transmission command signal, and a coincidence detection that generates an output when the content of this N-ary counter reaches a fixed value set on each receiving side. and means for resetting the N-adary counter to a predetermined content using the output of the means for selectively receiving the transmitted reset signal, and the output of the coincidence detecting means and the selectively received transmission command signal. AND gate each output, and this AN
A power line carrier communication system equipped with a receiving section that uses the D gate output as the output of the command signal sent from the transmitting side.