SU1084772A1 - Interface - Google Patents

Abstract

1. A DEVICE FOR PAIRING, containing a block of buffer registers, a group of inputs of which is the first group of information inputs of a device, a block of transmitters, a group of outputs of which is the first group of information outputs of a device, a block of receivers, a group. inputs and a group of outputs of which are, respectively, the second groups of information inputs and outputs of the device, an interrupt unit, the first and second groups of inputs of which are connected respectively to a group of outputs of the transmitter unit and the receiver unit, and the output is the output of the device interrupt, the clock generator whose output is connected to the first input of the interrupt unit and through the delay element with its second input, characterized in that, in order to simplify and expand the scope, it contains a task block frequency and delay times and a synchronization unit, a group of information inputs and a group of outputs of which are connected respectively to a group of inputs of a block of buffer registers and a group of inputs of a block of transmitters, the first and second outputs of a block for setting frequency and delay i are connected respectively | / Л with the control inputs of the clock generator and the gate element JC, the holder, the output of the clock generator is connected to the control input of the synchronization unit.

Description

2, the apparatus according to claim 1, characterized in that the synchronization unit contains a group of cells, each of which is composed of two AND elements, an HE element and a trigger, wherein the outputs of the trigger cells jecex form a group of outputs of the block. ka, the first and second inputs of the trigger in each cell are connected respectively to the outputs of the first and second elements AND, the first input of the first element AND through the element is NOT combined with the first input of the second element. And, the second inputs of the first and second elements and all the cells are combined and form Ktsy block input, the first inputs of the first elements And all the cells form a group of information input block.

The invention relates to computing and can be used, for example, to interface a computer with a group of alphanumeric displays. 1 A device for coupling comprising a receiver unit, a transmitter unit, an interrupt node, subscriber switches, an output registers unit, a decryption unit and a control unit that interconnects between the computer and the connected main terminals l. The drawback of the device is a large amount of equipment. Closest to the present invention is a device for COLLECTING, containing a block of buffer registers, a node of transmitters, receivers. clock generator, clock amplifier, clock drivers, clock transmission lines, clock drivers, clock transmission lines, delay element and interrupt unit 2. The disadvantages of the known device are the narrow area of its application, since the docking of displays according to this Scheme leads to the introduction of hardware changes to the boards of the serial interface of the displays, which is not always possible due to the different types of these boards, as well as the presence of a transmission channel of clock pulses, which complicates the device, i.e. It is necessary to have a transmission line of sync pulses and synchro pulses forming devices serving this line. All this leads to certain difficulties when docking various types of displays and computers. The aim of the invention is to simplify the design of the device and expand its scope by synchronizing the output information regardless of the operation of the displays. The goal is achieved by the fact that the device for pairing contains a block of buffer registers. a group of inputs of which is the first group of information inputs of a device, a block of transmitters, a group of outputs of which is the first group of information outputs of a device, a block of receivers,. a group of inputs and a group of outputs of which are, respectively, second groups of information inputs and outputs of the device, an interrupt unit, the first and second groups of inputs of which are connected respectively to the group of outputs of the transmitter unit and the receiver unit, and the output is the output of the device interrupt, sync pulse, output which is connected to the first input of the interrupt unit and through the delay element to its second input, a frequency and time delay unit and a synchronization unit, a group of information in the The first and second outputs of the frequency setting block and the delay time are connected respectively to the control inputs of the clock generator and the delay element, the clock generator output is connected to the control input of the block sync. In this case, the synchronization unit contains a group of cells, each of which consists of two AND elements, a NOT element and a trigger, and the trigger outputs of all cells form a group of block outputs, the first and second trigger inputs in each cell are connected respectively to the outputs of the first and second And elements, The first input of the first element AND through the element is NOT combined with the first input of the second element AND, the second inputs of the first and second elements AND of all the cells are combined, and form the control in the input of the block, the first inputs of the first elements AND of all the cells Braz group SEC DON information block. Due to the introduction of new units and communications, as well as the presence in each display of internal generators, which assign the operation of each board of the serial interface to a separate display, it was possible to refuse the transmission channel of sync pulses consisting of sync pulse amplifiers, sync pulse generator and sync transmission lines, and synchronize input information from the displays in the device itself. Thereby, it is possible to completely reject the operation of the display. This leads to the fact that there is no need to introduce any hardware changes into the serial interface boards of the displays, which allows connecting various types of displays with different types of serial interface boards to the computer. FIG. 1 shows a block diagram of the proposed device; in fig. 2 - one of the cells of the synchronization unit. The interface contains serially connected buffer register unit 1, the input group of which is the first group of information inputs 2 of the device, synchronization unit 3 and the transmitter unit 4, the output group of which is the first group of information outputs 5 of the device and connected to the first group information inputs of interrupt block 6, the output of which is the output 7 of device interruptions, block 8 of receivers, the group of inputs of which is the second group of information inputs of the device, and the group of outputs The second is the second group of information outputs 10 of the device and is connected to the second group of information inputs of the interrupt block 6, a pulse sync generator 11 whose output is connected to the first control input of the interrupt block 6, to the control one, to the input of the synchronization block 3 and to the first input delay element 12, the output of which is connected to the second control input of the interrupt unit 6 and the frequency setting and time delay unit 13, the first and second outputs. which are connected respectively to the control inputs of the generator 11 clock pulses and the delay element 12. I, Synchronization unit 3 consists of a group of cells, each of which contains two elements AND 14 and 15, an element 16 and a trigger 17, the output of which is the information output 18 of the synchronization unit 3, while the input of the first element 14 is connected through the element 16 with the first input of the second element 15 and is the information input 19 of the synchronization unit 3, the second input of the first element 14 is connected to the second input of the second element 15 and is the control input 20 of the synchronization unit 3, and the output of the first element. ment And 14 is connected to the first input igger 17, the second input of which is connected to the output of the second element And 15. The device operates as follows. . Information from the displays goes to the first group of information inputs 2 of the device and passes through the block 1 of the buffer registers, goes to the corresponding inputs of the synchronization unit 3, from which information synchronized by the pulses from the clock generator 11 is fed to the corresponding inputs of the transmitter unit 4, From the output of the latter, information suitable for processing in a computer is fed to the first group of information outputs 5 of the device. For proper operation of the device, it is necessary that the pulse frequency produced by the generator 11 clock pulses be equal to the pulse frequency of the internal display generators. The required frequency of the generated pulses is set by block 13 on the first output. On the second output of the block 13 set the required amount of delay. sync pulses required for reliable reception of information in a computer, the synchronization of input information in block 3 is as follows. From block 1 of the buffer registers via information output 18 of block 3 synchronization asynchronously. The information is fed to the first input of the first element AND 14 and through the element NOT 16 to the first input of the second element AND 15. Signal levels that are present at the first inputs of the elements AND 14 and 15, allow the passage of clock pulses that are received through control input 20 of synchronization unit 3 to second inputs of elements 14 and 15 from the output of generator 11 of clock pulses either through element 14, or through element 15, the outputs of which control the operation of trigger 17 The impulses coming from the outputs of the elements 14 and 15 to the corresponding inputs of the trigger 16, transfer it either to a single one, because to the zero state, depending on the input information, sent to the information input 19 of the 3 synchronization. At the output of the rigger 17, the information appears; the otor completely repeats the input information, since the frequency of the clock pulses coming from the clock generator ll is equal to the frequency of the internal display generators and strictly synchronized by the clock pulses of the clock generator 11, then, it is controlled by those Generator 11 clock pulses named after them, From the output of trigger 17, information is synchronized through the information outputs 18 of the synchronization unit 3 to the corresponding inputs of the transmitter unit 4.

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Thus, the device allows to synchronize the input information regardless of the operation of the displays and connect it to the EV14. Displays of various types with any boards in series with the interface.

The proposed technical solution eliminates the transmission channel of the sync pulses, which leads to a reduction in the equipment and the abandonment of the expensive coaxial cable used to transmit sync pulses.

FIG. g

Claims (2)

1. A device for interfacing, containing a block of buffer registers, the group of inputs of which is the first group of information inputs of the device, the block of transmitters, the group of outputs of which is the first group of information outputs of the device, block of receivers, group. the inputs and the group of outputs of which are respectively the second groups of information inputs and outputs of the device, the interrupt block, the first and second groups of inputs of which are connected respectively to the group of outputs of the transmitter block and the receiver block, and the output is the interrupt output of the device, the clock generator whose output is connected to the first input block interrupt and through the delay element with its second input, characterized in that, in order to simplify and expand the scope, it contains a job block often you and the delay time and synchronization unit, the group of information inputs and the group of outputs of which are connected respectively with the group of outputs of the block of buffer registers and the group of inputs of the block of transmitters, the first and second § outputs of the unit for setting the frequency and time | The delay menus are connected, respectively, but with the control inputs of the clock generator and the delay element, the output of the clock generator is connected to the control input of the synchronization block. FIG. 7 2, device pop. 1, characterized in that the synchronization unit contains a group of cells, each of which is made up of two And elements, an NOT element and a trigger, and the outputs of the triggers of all the cells form a group of outputs. ka, the first and second inputs of the trigger in each cell are connected respectively to the outputs of the first and second elements AND, the first input of the first element AND through the element is NOT combined with the first input of the second element. And, the second inputs of the first and second elements and all cells are combined and form control input of the block, the first inputs of the first elements AND of all cells form a group of information input of the block.