JPS59101016A - Magnetic recording circuit - Google Patents

Abstract

PURPOSE:To perform pulse train recording which can be formed into a one- chip IC with a simple circuit configuration, by making an electric current of one direction or opposite direction flow into heads connected between two switching circuits. CONSTITUTION:A clock and pulse-width setting pulse Ps shown in the diagram are added to each terminal 4, 5, and 6 and data D0 are added to a terminal 7. The data D0 are serial data, in which data successively recorded by heads 11- 14 are arranged in the order, and synchronized to a clock phi1. The cycle of a clock phi2 represents the one cycle of the serial data D0 and the clock phi2 is added in a rate of, for instance, one piece to four pieces of the clock phi1. The pulse Ps is to determine the pulse width of a pulse current +I or -I to be made to flow to each head and synchronized to the clock phi1. It is possible to make to flow a pulse-like current +I or -I of positive or negative polarity shown by g-t of the diagram to each head 11-14 in accordance with the ''H'' and ''L'' of the data D0.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a magnetic recording circuit for recording on multi-tracks of a magnetic recording medium by pulse train recording.

BACKGROUND TECHNOLOGY AND PROBLEMS When performing digital magnetic recording, normally a residual magnetization pattern as shown in Figure 1B is created on a magnetic tape by passing a rectangular wave alternating current as shown in Figure 1A through the head. I try to record it.

On the other hand, instead of the above-mentioned rectangular wave current, as shown in Fig. 1 Cζ, by flowing a positive and negative pulse train current to the head so that the envelope shown by the dotted line is equal to the above-mentioned rectangular wave, the pulse interval can be adjusted appropriately. It is known that if the residual magnetization pattern is selected to be approximately the same as that shown in FIG. This method, called pulse train recording, reduces crosstalk,
It has advantages such as reduced power consumption.

When performing digital recording on multi-tracks on a magnetic tape, if normal square wave recording is performed as shown in Figure 1, the current flowing through each channel will be continuous, which will complicate the drive circuit and reduce power consumption. increase When performing pulse train recording, a current source and a drive circuit that are turned on and off based on digital data are required for each channel, resulting in a complicated circuit configuration. Particularly in the case of tape recorders that record digital audio signals, which have been developed in recent years, for example, 16-bit data is
Since recording is performed on a track, the circuit scale becomes extremely large, making it extremely difficult to realize.

OBJECTS OF THE INVENTION In view of the above-mentioned problems, the present invention provides a magnetic recording circuit which performs pulse train recording with a simple circuit configuration and which can be integrated into a single chip IC.

SUMMARY OF THE INVENTION The present invention connects a plurality of switch circuits in which first and second switching elements are connected in series in parallel between a power supply and a reference potential. The heads are respectively connected between the connection points of the switching elements of the two adjacent switch circuits, and the first switching element of one of the two adjacent switch circuits is turned on and the second switching element of the other is turned on.
The head connected between the two switch circuits is turned on by turning on the switching element, or by turning on the second switching element and turning on the other first switching element. A magnetic recording circuit that allows current to flow in one direction or the opposite direction.

Example 8B1, SA2 and SB2...
... n series circuits of 8An and 8Bn are connected, and n heads (11) are connected between the connection midpoints of each series circuit.
(12) Both ends of (1n) are connected.

For example, by turning on the switches 8A4 and SB6 as shown, a current of 1 I flows through the head (13) as indicated by the solid arrow. Further, by turning on sA5 and SB4, a current -■ flows through the head (13) as indicated by the dotted arrow. This current +1 or -I is sequentially applied to the heads (11) to (1n) for a predetermined period of time. For this purpose, the eight switches 18B1 to 5An8Bn are sequentially controlled according to the data to be recorded. in this case,
For example, the head (11) is turned off, then the head (12)
When the head (1,) is energized again after a cycle of energization through (1n), the magnetization pattern caused by the previous energization and the magnetization pattern caused by the next energization are made to be continuous on the tape. For this purpose, a current consisting of a pulse train of a predetermined frequency and a predetermined pulse width as shown in FIG. 1C is applied to one head. Therefore, if the pulse train shown in FIG. These pulses are sequentially applied at staggered timings. That is,
One head among the heads (11) to (1n) is always energized.

FIG. 6 shows an embodiment of the invention applying the above principle.

Figures 4 - 2 show the output waveforms of points 0 to 0 in Figure 6.

In this embodiment, recording is performed on the first to fourth tracks on the tape by sequentially flowing current +I or -■ to four heads (11) to (14).
Both ends of X14) are connected between the connection midpoints of the MO8 transistors QA1%QB2 to QA5%QB5 connected in series. QA1 to QA5 are switch 8 in Figure 1.
% Q81 to QB5 correspond to the switches 8B1 to SB5 in the figure. The switch circuit of the above MO8I-transistor has a terminal to which a power supply voltage of 1 B is applied (
2) and ground through a current source resistor R. Therefore, for example, when QAl and QB2 are turned on, a current flows through the head (11), and QA2 and QB1 are turned on.
When turned on, a current of 10cm flows through the head (11).

A clock φ2 and a pulse width setting pulse P shown in FIG. 4 are applied to terminals (4) (51 and (6), respectively, and data Do is applied to terminal (7). This data D is This is serial data in which data sequentially recorded by the heads (11) to (14) are arranged in sequence, and is synchronized with the clock φ1.The period of the clock φ2 is one period of the serial data Do, that is, the data is T indicates the recording period from the first track to the fourth track, and in this embodiment, it is added at a rate of one for every four clocks φ1.The above pulse PS is a pulse current +■ or - applied to each head. It determines the pulse width of (2) and is synchronized with the clock φ1.The clock φ1 is applied to the clock terminal CK of the D-type logic block (hereinafter referred to as FF) (8) (9) C0) aυ, and the clock φ2ζ It is added to the D terminal of FF (8). Ql, C2, Q of each FF (8) ~ aω
The five outputs are respectively applied to the D terminal of the next stage FF. Therefore, the Ql - QA output pulse of each FIi'' (87 to <11) is substantially the one period of the tally φ2 and the tally φ1 shifted by one period. ) indicates the timing at which the current is caused to flow through the pulse P5 corresponding to each output pulse, and +■ or -■ is caused to flow depending on the data during the period of the pulse P5 corresponding to each output pulse.

For this purpose, each of the above Q, ~q output pulses and pulse P
, and Data D. and gate (13) (24) (
15) (Add to 1ω. These AND gates 03)
-C6) output is sent to the husband heads (11) to (14) +
Data D is applied to each head, indicating the timing for flowing current I.

It appears as a pulse that corresponds to rHJ of and has a pulse width equal to that of the pulse Ps.

That is, by turning on Ql31 with the output of AND gate (13) and turning on QA2 through 2υ, the current data Do is sent to the head (11).
A current flows to record "I(").Also, the output of AND gate Q4) is the OR gate c! 4J (221 respectively to turn on Ql2 and QA3, and gate (1
The output of 5) turns on Ql3 and QA4 through the OR gate (25+C23), and the output of the AND gate (161 turns on Ql4 through the OR gate (26)).
is turned on and %QA5 is turned on. As a result, current +1 flows through the heads (12) to (14).

Each of the above Q1-Q4 output pulses and pulse P.

and data Do are inverted using an inverter (2 forces) and are applied to AND gates (17) (18+ tts). This indicates the timing of flowing the current (rL) of the data Do applied to each head.
It appears as a pulse corresponding to J and having a pulse width equal to that of pulse P5.

In other words, by turning on 9 people 1 with an output of 1η and forming an or game (or game) (247F- to turn on all 2 QB2), the current data Do is sent to the head (11).
A current -I that records rLJ flows. Also, the output of AND gate 0 turns on QA2 b Ql3 through OR gates CI'1) (25) F-, and the output of AND gate a9 turns on QA3, Ql3 through (22) and (26), respectively.
Ql4 is turned on, and the output of the AND gate (20) turns on QA4 through the OR gate (2), and QB57j is turned on.This causes current to flow to the heads (12) to (14). -■ flows.

According to the above configuration and operation, each head (11) to (14)
), as shown in Fig. 4, a pulsed current of positive or negative polarity is applied to rHJ r of data Do.
It can flow according to LJ.

The recording circuit shown in FIG. 6 can be configured to select the head to be operated from among the heads (119 to (14)).

In that case, as shown in FIG. 5, the pulse Ps and the head selection signal P as shown in FIG.
Just add it to the terminal in the figure (point 61C). Incidentally, the signal PE shown in FIG. 4 becomes rLJ during the period of the Q4 output pulse shown in the same figure @.

Therefore, in this case, the head (13) is not operated and the third
By selectively setting rLJ to the falling period corresponding to the Ql, C2, and QA output pulses of the external signal P8 when data Do is not recorded on the track, the head to be operated can be arbitrarily selected.

In the recording circuit shown in FIG. 6, when the head current pulse is cut off, a transient current is generated due to the inductance of the head, which may cause &tJ'J ringing or the like. As a countermeasure for this, as shown in Fig.
・・・・・・・・・・・・Switch SC1%SC2...
・・・・・・－・・・・・・・・・ are connected in parallel. By turning each switch off when the head current is flowing as shown in Figure 7, and turning it on just before the head current is completely cut off, the above transient current can be completely absorbed through each switch. .

In the recording circuit shown in FIG. 6, a common current source made of a resistor R is provided to a plurality of switch circuits made of MOS transistors, but this current source may of course be made of an active element such as a transistor. be. In addition, as shown in FIG. 8, current sources (281) (28□
(28n) may be provided.

In the recording circuit shown in FIG. 6, current is sequentially applied to the heads (11) to (14), and the first, second, etc.
Although recording is performed in the order of the n-th track, recording may be performed in any order depending on the situation.

In that case, the connection of the Q1Q4 output pulses added to the AND gate α-(20) may be changed depending on the recording order.

Effects of the Invention Since both ends of a plurality of heads are connected between a common power source and a reference potential, the number of wiring lines is small. That is, in the case of n heads, the number of wires between the heads and the recording circuit is n1,000. The structure of the intelligent logic circuit is simple. Therefore, it is possible to realize a 1-nap IC circuit with low power consumption without increasing the circuit size. Especially when using a thin film head, it is possible to integrate the head and the recording circuit.

[Brief explanation of drawings]

Figure 1 is a waveform diagram to explain pulse train recording.
Fig. 2 is a circuit diagram showing the principle of the present invention, Fig. 6 is a block diagram showing an embodiment of the invention, Fig. 4 is a time chart of Fig. 6, and Fig. 5 is a diagram showing the operation head selection. A circuit diagram showing an embodiment, FIG. 6 is a circuit diagram showing an embodiment of a circuit for preventing ringing, FIG. 7 is a time chart explaining the operation of the sixth factor, and FIG. 8 shows another embodiment. In the circuit diagrams, the symbols used in the drawings are (11) to (1n) - Head QA 1
~QAn・・・・・・・・・MOS) transistor Q]'
! 1 to Qan... are MOS transistors. Agent Masaru Saturn Yoshio Tsuneko Toshiki Sugiura Figure 1 Figure 2 10 Figure 4 ■ 8--]-7-

Claims (1)

[Claims] A plurality of switch circuits formed by connecting first and second switching elements in series are connected in parallel between a power supply and a reference potential, and between the connection points of the first and second switching elements of each switch circuit. The head is connected to the
The first switching element of one of the two adjacent switch circuits is turned on and the second switching element of the other is turned on, or the second switching element of one of the two adjacent switch circuits is turned on and the other one of the switching elements is turned on. A magnetic recording circuit configured to cause current to flow in one direction or the opposite direction through a head connected between the two switch circuits by turning on the first switching element of the magnetic recording circuit.