JPS59100556A - Lsi chip - Google Patents
Lsi chipInfo
- Publication number
- JPS59100556A JPS59100556A JP57211565A JP21156582A JPS59100556A JP S59100556 A JPS59100556 A JP S59100556A JP 57211565 A JP57211565 A JP 57211565A JP 21156582 A JP21156582 A JP 21156582A JP S59100556 A JPS59100556 A JP S59100556A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- lsi
- projections
- printed circuit
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15162—Top view
Abstract
Description
【発明の詳細な説明】
く技術分野〉
本発明は中央演算処理機（ＣＰＵ）、リードオンリメモ
リ（ＲＯＭ）、リードライトメモリ（ＲＡＭ、）、入出
力インターフェース（Ｉｌｏ）等のＬＳＩチップＣで関
するものである。[Detailed Description of the Invention] Technical Field> The present invention relates to an LSI chip C such as a central processing unit (CPU), read-only memory (ROM), read-write memory (RAM), input/output interface (Ilo), etc. It is something.
〈従来技術〉
前記ＣＰＵ、ＲＯＭ、ＲＡＭ、Ｉｌｏ等のＬＳＩチップ
はマイクロコンピュータシステムを構成する電子部品群
であるが、一般にこれらの電子部品はプリント基板上に
搭載して電気的且つ機械的に結合される。したがって、
従来システム開発にあたってプリント基板の役割が不可
欠となるために、設計に長時間を要し而も設計変更の自
由度に著しく乏しいという欠点があった。また、プリン
ト基板を必要とするためにコスト高になるという欠点が
あったＯ
く目的〉
本発明はかかる従来の欠点に鑑み、各チップ相互間で直
接電気的且つ機械的に結合離脱できるようにして、プリ
ント基板なしでマイクロコンピュータシステムを構成で
きるＬＳＩチップの提供にある。<Prior art> LSI chips such as the CPU, ROM, RAM, Ilo, etc. are a group of electronic components that constitute a microcomputer system, and these electronic components are generally mounted on a printed circuit board and electrically and mechanically connected. be done. therefore,
Conventionally, since the printed circuit board plays an indispensable role in system development, it takes a long time to design, and there is a considerable lack of freedom in design changes. In addition, there was a drawback that the cost was high due to the need for a printed board. The object of the present invention is to provide an LSI chip that can configure a microcomputer system without a printed circuit board.
〈実施例〉 以下図にもとづいて本発明の詳細な説明する。<Example> The present invention will be explained in detail below based on the drawings.
第１図は本発明に係るＬＳＩチップとその結合状態を示
す図である。図において、Ａｏ乃至Ａ５はそれぞれ本発
明のＬＳＩチップを示し、たとえばＡ。はＣＰＵチップ
、Ａ１ はＲＯＭチップ、Ａ２はＲＡＭチップ、・・・
Ａ５はＩ１０チップである。FIG. 1 is a diagram showing an LSI chip according to the present invention and a state in which they are connected. In the figure, Ao to A5 each indicate an LSI chip of the present invention; for example, A. is the CPU chip, A1 is the ROM chip, A2 is the RAM chip, etc.
A5 is an I10 chip.
これらチップは後述する結合手段により相互に電気的且
つ機械的に結合されて一つのマイクロコンピュータシス
テムを構成している。These chips are electrically and mechanically coupled to each other by coupling means to be described later to constitute one microcomputer system.
次に、代表的なＣＰＵチップＡ。について本発明チップ
の具体的な構造を説明する。チップＡ。Next, a typical CPU chip A. The specific structure of the chip of the present invention will be explained below. Chip A.
は直方体に形成されていて内部にはＬＳＩ（ＣＰＵ）Ｔ
７ か埋設されている。また、このチップＡ。の隣り
合う一組の側基には突起Ｘ。、Ｙｏが形成され、今一つ
の一組の側基には前記突起と嵌着関係にある凹部ＸＩ’
Ｎ、ＹＩＮか形成されている。前記各突起と四部には埋
設したＬＳＩ（Ｌｏ）のパスラインに接続された複数本
の接触子Ｐ。が配設されている。is formed into a rectangular parallelepiped, and there is an LSI (CPU) T inside.
7 are buried. Also, this chip A. A pair of adjacent side groups have protrusions X. , Yo are formed, and another set of side bases has a recess XI' in a fitting relationship with the projection.
N, YIN are formed. A plurality of contacts P are connected to the path lines of the LSI (Lo) buried in each of the protrusions and the four parts. is installed.
たたし、第２図に示すように突起Ｘ。、Ｙｏの接触子Ｐ
は該突起の表面に露出形成され、凹部ｘＩＮＹｌＮの
接触子Ｐ。は今一つのＬＳＩチップの接触子Ｐ２と同様
に前記突起の接触子に弾性的に接触する弾性片にて図示
の如く設けられている。However, as shown in FIG. , Yo contact P
is formed exposed on the surface of the protrusion, and is a contact P of the recess xINYIN. As shown in the figure, is an elastic piece that elastically contacts the contactor of the protrusion, similar to the contactor P2 of another LSI chip.
第３図はチップ相互間の結合状態を強化させた例であり
、この例ではチップＡ。の四辺部にそれぞれ図示のよう
な形状の凹部ＸＩＮ、ＹＩＮとこの凹部に嵌着関係にあ
る凸部Ｘ。、Ｙｏを設けるとともに、各凹凸部の基面に
はＴ１．Ｔ２のように内部のＬＳＩ（Ｌ）のパスライン
に接続された導電性のパターンが形成されている。FIG. 3 shows an example in which the bonding state between chips is strengthened; in this example, chip A is used. Concave portions XIN and YIN each having a shape as shown in the figure and a convex portion X that fits into the concave portions on the four sides thereof. , Yo are provided, and the base surface of each uneven portion is provided with T1. A conductive pattern connected to the pass line of the internal LSI (L) is formed like T2.
上述したチップのパスラインの配設状態は第４図及び第
５図に示す通りである。即ち、ＬＳＩへのパスラインＢ
乃至Ｂ５はチップの四辺に設けられ、どの方向に接続
されたチップのＬＳＩとも各パスラインが共通に接続さ
れるようになっている。特に第５図はフィルムキャリア
方式によるもので、各四辺のパスラインは両面パターン
により接続され、ＬＳ Ｉ％の接続が各１ケ所だけで済
むようになっている。図では表裏のパターンを実線と破
線で区別して結線している。The arrangement of the pass lines of the chip described above is as shown in FIGS. 4 and 5. That is, the path line B to the LSI
B5 to B5 are provided on the four sides of the chip so that each pass line is commonly connected to the LSIs of the chip connected in any direction. Particularly, FIG. 5 uses the film carrier method, and the pass lines on each of the four sides are connected by double-sided patterns, so that only one connection for each LSI % is required. In the figure, the front and back patterns are distinguished and connected using solid lines and broken lines.
第６図は第５図の断面図を示すもので、機械的強度を確
保すべくベース基材Ｚ上にフィルムキャリアーＦＰＣに
接続したＬＳＩを図示の如く貼付てコーテイング材Ｃ８
で被覆されている。ＰＷｏ。FIG. 6 shows a cross-sectional view of FIG. 5, in which an LSI connected to a film carrier FPC is pasted on a base substrate Z as shown in the figure to ensure mechanical strength, and a coating material C8 is applied.
covered with. PWo.
ＰＷ、は前記フィルムキャリアーＦＰＣの表裏に形成し
たパターンである。PW is a pattern formed on the front and back sides of the film carrier FPC.
かかる構成のＬＳＩチップによれば、結合手段に・より
各チップを適宜結合でき、しかも結合と同時に各チップ
のＬＳＩのパスラインが共通接続される。したかって、
たとえば上記構成のＣＰＵチップＡ。、ＲＯＭチップＡ
、、ＲＡＭチップＡ２．Ｉ沖チップＡ３もしくはＡ５等
をプリント基板なしに電気的且つ機械的に結合して容易
にさまざまなマイクロコンピュータシステムを得ること
ができる。According to the LSI chip having such a configuration, each chip can be appropriately coupled by the coupling means, and the pass lines of the LSIs of each chip are commonly connected at the same time as coupling. I wanted to,
For example, CPU chip A with the above configuration. , ROM chip A
,,RAM chip A2. Various microcomputer systems can be easily obtained by electrically and mechanically connecting chips A3, A5, etc. without a printed circuit board.
そして、このシステムはＩ’１０チップＡ５のチップ」
二面に半田付した配線コードＣを介して電源や入出力機
器と結合できるようになっている。And this system is an I'10 chip A5 chip.
It can be connected to a power source and input/output equipment via a wiring cord C soldered on two sides.
−１−記チノブは相互にどの方向にも接続できるように
ハスラインが考慮されているが、この場金ＲＡＭチップ
にあっては予めアドレスをＰＬＡ等で固定してもよく、
また図示の如くＵ。とＵ、乃至Ｕ５のどれかを結合して
、たとえば６４にバイト単位でアドレスを切換えるよう
に処理してもよい。-1- The chinobu described above is designed with a lotus line so that it can be connected to each other in any direction, but for this in-place RAM chip, the address may be fixed in advance with PLA etc.
Also, as shown in the figure, U. It is also possible to combine any of U and U5 and to switch the address in byte units to 64, for example.
また、前記各チップの結合位置についてはたとえは、Ｃ
ＰＵチップの右横にＲＡＭチップチップ、下方ＫＲＯＭ
チップというようにある程度限定した形であってもよい
。更に結合手段については上記実施例に限定されない。Also, regarding the bonding position of each chip, for example, C
RAM chip on the right side of the PU chip, KROM below
It may be in a somewhat limited form such as a chip. Furthermore, the coupling means is not limited to the above embodiment.
く効果〉
以上の様に本発明のＬＳＩチップは結合手段を具えて、
各チップ相互間で適宜電気的且つ機械的に結合離脱でき
るようにしたから、プリント基板なしで容易にマイクロ
コンピュータシステムを構成することができ、プリント
基板の設計が全く不要となるので大幅なコストダウンを
はかることが出来る。Effect> As described above, the LSI chip of the present invention has the coupling means,
Since each chip can be electrically and mechanically connected and disconnected from each other as appropriate, a microcomputer system can be easily configured without a printed circuit board, and there is no need to design a printed circuit board, resulting in a significant cost reduction. can be measured.
第１図は本発明のＬＳＩチップとその結合状態を示す図
、第２図は同要部詳細図、第３図は他の実施例を示す図
、第４図及び第５図はパスラインのパターンを示す図、
第６図は第５図の断面図である。Fig. 1 is a diagram showing the LSI chip of the present invention and its connection state, Fig. 2 is a detailed view of the same main part, Fig. 3 is a diagram showing another embodiment, and Figs. 4 and 5 are diagrams of pass lines. Diagram showing the pattern,
FIG. 6 is a sectional view of FIG. 5.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57211565A JPS59100556A (en) | 1982-11-30 | 1982-11-30 | Lsi chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57211565A JPS59100556A (en) | 1982-11-30 | 1982-11-30 | Lsi chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59100556A true JPS59100556A (en) | 1984-06-09 |
Family
ID=16607888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57211565A Pending JPS59100556A (en) | 1982-11-30 | 1982-11-30 | Lsi chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59100556A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0283590A2 (en) * | 1987-03-18 | 1988-09-28 | Telenorma Gmbh | Electrical components |
| JPH01150348A (en) * | 1987-11-06 | 1989-06-13 | Ford Aerospace Corp | Interconnection system for integrated circuit chip |
-
1982
- 1982-11-30 JP JP57211565A patent/JPS59100556A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0283590A2 (en) * | 1987-03-18 | 1988-09-28 | Telenorma Gmbh | Electrical components |
| US5006920A (en) * | 1987-03-18 | 1991-04-09 | Telenorma Telefonbau Und Normalzeit Gmbh | Electrical components |
| JPH01150348A (en) * | 1987-11-06 | 1989-06-13 | Ford Aerospace Corp | Interconnection system for integrated circuit chip |
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