JPS59100353U - absolute value circuit - Google Patents

absolute value circuit

Info

Publication number
JPS59100353U
JPS59100353U JP19507482U JP19507482U JPS59100353U JP S59100353 U JPS59100353 U JP S59100353U JP 19507482 U JP19507482 U JP 19507482U JP 19507482 U JP19507482 U JP 19507482U JP S59100353 U JPS59100353 U JP S59100353U
Authority
JP
Japan
Prior art keywords
absolute value
value circuit
output
terminal
rectifying element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19507482U
Other languages
Japanese (ja)
Inventor
博康 佐々木
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP19507482U priority Critical patent/JPS59100353U/en
Publication of JPS59100353U publication Critical patent/JPS59100353U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来の絶対値回路図、第2図第3図は、その
動作を、説明する信号波形図、第4図は、本考案による
絶対値回路の一実施例回路図、第5図は、その動作を説
明する信号波形図、第6図は、本考案による、他の実施
例の回路図である。 1〜6・・・端子、io、ii・・・演算増幅器、20
〜24・・・整流素子、30〜38・・・抵抗、■1〜
V6・・・波形例、−■・・・負電源端子、+謀・・・
正電源端子。
FIG. 1 is a conventional absolute value circuit diagram, FIG. 2, FIG. 3 is a signal waveform diagram explaining its operation, FIG. 4 is a circuit diagram of an embodiment of the absolute value circuit according to the present invention, and FIG. The figure is a signal waveform diagram explaining its operation, and FIG. 6 is a circuit diagram of another embodiment according to the present invention. 1 to 6... terminal, io, ii... operational amplifier, 20
~24... Rectifying element, 30~38... Resistor, ■1~
V6... Waveform example, -■... Negative power supply terminal, + plot...
Positive power terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 反転信号と非反転信号を出力する2個の演算増幅器の出
力端子のおのおのに、2個の整流素子を同極性出力が得
られるよう接続し、片方の整流素子を、演算増幅器の負
帰還回路のに接続し、もう一方の整流素子を、ひとつの
端子に接続して、出力端子とすることを特徴とする絶対
値回路。
Two rectifying elements are connected to each of the output terminals of two operational amplifiers that output an inverted signal and a non-inverting signal so that outputs of the same polarity are obtained, and one rectifying element is connected to the negative feedback circuit of the operational amplifier. An absolute value circuit characterized in that the other rectifying element is connected to one terminal and used as an output terminal.
JP19507482U 1982-12-24 1982-12-24 absolute value circuit Pending JPS59100353U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19507482U JPS59100353U (en) 1982-12-24 1982-12-24 absolute value circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19507482U JPS59100353U (en) 1982-12-24 1982-12-24 absolute value circuit

Publications (1)

Publication Number Publication Date
JPS59100353U true JPS59100353U (en) 1984-07-06

Family

ID=30419094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19507482U Pending JPS59100353U (en) 1982-12-24 1982-12-24 absolute value circuit

Country Status (1)

Country Link
JP (1) JPS59100353U (en)

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