JPS5898895A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption and reduce the increment of the number of elements, by arranging memory cells, where polysilicon resistances are used as loads, in a matrix and supplying power commonly to plural cells through a current limiter where the resistance is lowered by the rise of temperature. CONSTITUTION:Memory cells M11-Mmn where polysilicon resistance elements are used as load resistances R1 and R2 of MOSFETs T1 and T2 are arranged in a matrix to constitute a memory cell array 21. Current limiters 22 where resistance values are raised by the rise of temperature are constituted with, for example, MOSFETs to supply power commonly to plural memory cells. Thus, the power consumption is reduced, and the increment of the number of elements is reduced considerably to make them into an integrated circuit with advantage because the current limiter is used commonly for plural memory cells.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor annual rate circuit having a memory cell using a polysilicon resistor as a load element.

Technical background of the invention and its problems MO3 type static RAM (Random Acc
essMemory) is beginning to realize the realization of long-term iodization and low power consumption of circuits by using high-resolution anti-polysilicon monolayers as load elements of memory cells.

However, silicon itself is a semiconductor, and its resistance value has a negative slope with temperature. Moreover, the value of polysilicon resistance changes exponentially with temperature. Therefore, at high temperatures, the value of polysilicon is extremely lower than that at low temperatures, leading to an increase in the value of the power flowing from the source vc0, and an increase in the power consumption of the integrated circuit. arise.

The current that flows through the polysilicon resistor element during the first wake-up period is a current flowing through the polysilicon resistor element, especially in the case of a semiconductor memory, to reduce power consumption not only during operation but also during standby.

r1 Figure 1 is a conventional example of MO8 type static RAM,
TIyT2 is a drive MO8) run disk, R1 and R2 are load resistance elements made of polysilicon, D and D are data connectors, 'r3 and T4 are MO3) run disks for output transfer.
QC* “8B is the power supply.

The above resistance R,=:R2, and the transistor T+
When the first rule is on (tracing), M and the flow through the resistor R1 are as follows:
The current is approximately equal to the current flowing through the resistor R2 when the transistor T2 side is on. In FIG. 1, the current consumption in this memory cell is 1=vcc/R1, and the resistance R1 is sensitive to temperature changes and is within an exponential range. Since it changes with , it can be expressed as . However, experimentally with Ea active energy
'j' 0.3 to 0.5 [eV], α is a constant, K is Boltzmann's constant, and T is absolute relative to temperature. Therefore, as the hot water temperature rises, the current consumption decreases by the amount corresponding to the decrease in polysilicon resistance1. -For example, if we consider Bit's memo IJ-1.6, at room temperature (25℃) Resistance R at (25℃) Total R
+(25℃) = 1. If [CΩ], then the constant ゛,
If the heavy current is 11' at (25°C) and vcc = 5V, then I+ (25°C) = 5x]0 [A], which is 16424% I for all memory cells, which is now 80 [μA]. On the other hand, at high temperatures such as 80°C, Ea = 0.4 [
eV] f h f'f, R, (1°C): R1 (25
°C)/e 24°R1 (25°C)/1°, and the current consumption in all memory cells is 800 [μA]. Therefore, in a 64-bit memory, the current consumption is four times that of a 16-bit memory with the same resistor 9-wire, and even four times that amount in a 256-bit memory, so that the current consumption continues to increase.

In order to reduce the above-mentioned dissipation current or keep it at the same level, it is necessary to increase the resistance value of the load resistance element.

In order to increase the polysilicon resistance value, the shape of the polysilicon resistor can be made elongated, or the polysilicon resistor itself can be manufactured to have a high sheet resistance value. It becomes an obstacle to integration,
In addition, increasing the sheet resistance of polysilicon resistor
There is a problem with manufacturing technology.

In order to improve the above problem, a current limiter may be inserted at the power supply end of the memory cell.

For example, as shown in Figure 2, a memory cell and a power supply. . It is sufficient to insert a depression resistor MO8l-transistor Tll between the I and the end of the ship.

The transistor Tll in the memory cell operates as a constant current element, in other words, a current limiter. In this case, the current flowing through the memory cells is 1 = ■ o (composite current), and if there are n memory cells, n x r 11 = r o. For example, if all bits are connected to 16, it can be expressed as shown in Figure 3 on the same side. On the other hand, I 6 = K
V 7H” eff −V TH=·(2).

Here, K is fixed, COx is the gate density per the area of the crown,
W is the channel width, Teff is the effective electron mobility, and VTH is the threshold voltage. From the above equation, in the circuit of Figure 2 I, even if the resistance of resistor R3 decreases at high temperature, the mobility 1leff,
Since it has the opposite characteristic to polysilicon resistance, which decreases with increasing temperature, the current flowing through the memory cell is μef
It will be repaired as f decreases, and ftjl is limited. Note that the above-mentioned current (2) is similarly limited by TH and the dimensions Z, W of the transistor T11.

In this way, according to the configuration shown in Fig. 2, it is possible to compensate the temperature characteristics of the polysilicon px load resistance by the mobility/'eff, and therefore, when a high p, 2 second memory is used. However, the memory of low consumption aerodynamics is fil, 1
It is something that can be created.

Figure 4 1 to 6 Figure 1 Figure 2 (Improvement of tll 9
ij, ff'4 diagram is an example of using the enhancement type transistor T21 as a vine for τ to flow. In this t'' case, when r1 degree increases, the effect of decreasing the eff of the transistor T21 is Therefore, the result of D1 which is in phase with the male side is ↓).

In Figure 5, an enrichment type or depletion type trunk nut T31e is used as a forward flow limiter, and a clock signal 4 or some kind of limiter, C'',
This is an example of Saiichigo who supplied 70. In this case as well, the effects that are in phase with each of the above-mentioned components F fjj are suppressed.

FIG. 6 1 shows an example in which a depletion type transistor T11°T//1 is used in parallel with the case shown in FIG. 2 as a current limiter.

Note that the current limiter is not limited to the above-mentioned case; for example, a normal resistance element whose resistance value increases as the temperature rises may be used.

However, if the limiter is provided for each memory cell in the memory cell array, the number of elements will increase to 7 elements/cell, There is an obstacle to privatizing Akanesu.

OBJECTS OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a semiconductor integrated circuit that can improve the above-mentioned problem of poor consumption without increasing the number of elements.

Analysis of the invention As shown in each of the circuits 1 and IK described above, a memory cell array in which memory cells using polysilicon resistive elements as square grids are arranged in a matrix (one row and one column) is used. In a semiconductor integrated circuit having a semiconductor integrated circuit, power is commonly supplied to multiple memory cells via a current limiter as a constant current element. 1 in line
There are cases where it is fixed, such as when it is fixed, when it is fixed by column, when it is fixed as one across multiple rows and multiple columns of the memory cell array, and so on.

Effects of the Invention As described above, low power consumption becomes possible by supplying a power source to the memory cell via a current limiter whose resistance value actually decreases as the temperature rises. Furthermore, since the current limiter is commonly used for six memory cells, the increase in the number of elements (p) can be greatly reduced, which is advantageous in terms of packaging and circuitry.

Embodiment of the Invention An embodiment of the invention will be described below with reference to the drawings. Rabbit 7
The figures to FIG. 9 show each embodiment of the present invention, and M1
+-Mmn is a matrix memory cell array 21
Each memory cell, 2210~22mo r 22o+
~226nz 22 are weighted limiters. The above memory cell Ml, ~
Mmn and fly are respectively shown in the circuit of FIG. 2 (considered as a constant %, with the rotating transmitter section omitted). In the embodiment shown in FIG. 7, the power supply lines of the memory array 21 are arranged in a matrix, and a weighted limiter is inserted in each row, and in the embodiment shown in FIG. Embodiment 1 shown in FIG. 9 is one in which the power supply lines of the memory cell array are grouped into columns and a 1L weight limiter is inserted in each column.
The power supply line of the array 21 is made common across each row and each column.

By using the current limiter in common to the first memory cell and supplying power as described above, it is possible to configure the memory without changing the number of elements. If we consider a 16-bit memory as flI, the configuration of the memory cell array of an integrated circuit chip is 128 rows x 128
By using a common current limiter for each row, the number of transistors can be increased by 10-128 transistors, and by reversing the 1-current IJ transmitter for each column, it is possible to increase the number of transistors by 128 This can be done by adding the number of elements, and the rainbow shown in Figure 9 (in principle, if summed up over each matrix), @ 17) can be done by adding the number of prime numbers.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a memory cell of a conventional MO8-type static RM (Fig. 2 is a circuit diagram showing a memory cell designed to reduce project costs. Equivalent circuit diagrams, evaluation I Figures 4 to 6 are circuit diagrams showing other circuits designed to reduce power consumption, and Figures 7 to 9 are circuit cell diagrams of each embodiment of the present invention. .T1~T4...MOS) Lannostar, R1r R2
...Load resistance, "',"', T3+,'r,l
, T'/+t + 22. o~22mo, 2261
~220n, 22-... Hayabusa flow limiter, M11~Mmn
...Memory cell, 21...Memory cell array. Applicant Koihito Patent Attorney Suzue Takehiko 11- Figure 6 ■ SS Figure 9 cc

Claims (5)

[Claims] (1) In a semiconductor integrated circuit having a memory cell in which memory cells using polysilicon resistors as load elements are arranged in a matrix, at least one current whose resistance value increases as the temperature rises. Through a limiter? A semiconductor integrated circuit that is characterized by supplying power in common to memory cells. (2) The semiconductor integrated circuit 0 according to claim 1, wherein the memory cells of the above-mentioned Shona are grouped by row of the memory cell array. (3) The semiconductor integrated circuit according to claim 1, wherein the plurality of memory cells are grouped by column of the memory cell array. (4) The memory cell in the previous statement a chamber = h is the corner n
1. A semiconductor integrated circuit as set forth in Box 8F1 of the Patent Revision, which is assembled over a plurality of rows and columns of a memory cell array. (5) #The 1N semiconductor integrated circuit according to claim 1, in which the current distribution sum is an MO8 type transistor whose effective electron mobility decreases when the temperature decreases.