JPS5897741A - Data converting system - Google Patents

Abstract

PURPOSE:To eliminate a program for alternation of the data definition to simplify the program as well as to increase the system processing speed, by altering the data definition by means of a program of a bit parallel processor. CONSTITUTION:A data storing means 1 stores the bit parallel word series data PD, and an address information storing means 2 stores the address information RA which designates the output bit order of the bit series data SD. A register 3 holds the information RA. In this case, the information RA which is read out to the register 3 is used for a reading address of the next address information given from the means 2. The address is then read by one bit out of the means 2 based on the information RA which is held at the register 3. Thus the data SD is delivered.

Description

[Detailed description of the invention] The present invention relates to a data conversion method.

Bit-parallel word-serial data with a two-dimensional structure in which each digit (bit) constituting a word is processed in parallel and the word is processed serially multiple times is extremely common in the information processing field. It is a data format. On the other hand, bit-serial data with a one-dimensional structure in which each bit constituting the data is processed serially, one bit at a time, requires fewer interface lines to transport the data, as typified by data on a data communication line. This is a data format adopted for the purpose of

For example, when connecting a device that processes bit-parallel word-serial data to a device that processes bit-serial data, it is necessary to perform data processing in the bit-parallel word-serial data format followed by data processing in the bit-serial data format. In some cases, it may be necessary to convert bit-parallel word-serial data to bit-serial data.

In the conventional data conversion method, a bit-parallel processing device that processes bit-parallel word-serial data outputs one word at a time to a shift register so that the bit order of the bit-serial data can be maintained, and the shift register inputs and outputs one word to a shift register. Each bit of the received word is shifted one bit at a time and output.

By the way, there are cases where there is no agreement in data definition, that is, in the order of bit arrays, between the bit parallel processing device and the shift register. For example, in a bit-parallel processing device, the control information and the data subject to multiple control are arranged in a bit array such that they are concentrated in a group, whereas in a shift register, the bit-parallel processing , + Due to the convenience of the hardware configuration of the connection device of the shift register other than the physical device, the control information and the data that are subject to multiple controls therein form a plurality of groups, and the two types of groups are mixed in the input system. In such a case, in the conventional data conversion method, the program of the bit-parallel processing device converts the bit-parallel word-serial data into a bit-array that matches the data definition of the shift register. Since the data is converted into serial data and output to the shift register, it has the disadvantage of complicating the program and slowing down the system processing speed.

An object of the present invention is to provide a data conversion method that simplifies programs and improves system processing speed.The method of the present invention converts input bit-parallel word serial data into bit-serial data, bit by bit. In the data conversion method for outputting, a data storage means for storing the bit-parallel word-serial data, an address information storage means in which address information for specifying an output bit order of the bit-serial data is stored in advance; A register is provided for holding the address information read from the address information storage means after the bit parallel word serial data is stored in the data storage means, and the address information read into the register is stored as the address information. The next address information from the storage means is used as an address for reading, and the bit serial data is output by reading out one bit at a time from the data storage means based on the address information held in the register. ing.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows an application example of this embodiment.

The present application example includes a switching circuit 4, a selection circuit 5, an adapter 10 which is a bit parallel processing device, and a shift register 40.
11. Two data conversion devices 20, 21. Two maintenance panels 30, 31, two shift registers 40° 41. Two logical devices 50, 51, data communication line 100. Three interfaces 1l 1200, 201° 300 and 4
It is composed of sets of connecting wires 60, 70, 61, and 71.

Logic units 50 and 51 are connected to shift registers 40 and 41 . . . from maintenance panels 30 and 31, respectively. Maintenance signals for logic devices 50 and 51 can be received via connection lines 60 and 61 and 70 and 71, respectively. maintenance panel 30,
Since it is housed in the shift register 40, the connection line 6
0, 70. 61 and 71 can be short and many, and these connecting lines transfer multiple bits in parallel. This is typically how the maintenance panels 30 and 31 are connected to logic devices 50 and 71, respectively. Although the maintenance of the logical devices 51 is performed, the maintenance of the logical devices 50 and 51 can also be performed from a remote location via the data communication line 100. especially,
With the spread of information processing through data communications, the precision of such remote maintenance is increasing.

Data sent in bit series from a remote location (via data communication line 100) is transmitted to adapter 10 into a maintenance signal similar to the maintenance signal supplied to maintenance panel 30 or 31, respectively.
or 11, but this conversion process is performed in bit parallel. The adapters 10 and 11 are installed, for example, in the same computer room or at the user's workplace, but the adapters 10 and 11 are also designed to carry bit-serial data over the data communication line 100 and the interface lines 200 and 201. .

Data converters 20 and 21 convert bit parallel word and bit serial data in adapters 10 and 11, respectively, to interface lines 200t!, respectively. -201 bit serial data.

However, the data definition of the bit serial data on the interface lines 200 and 201 is the same as the shift register 40.
Although it is consistent with the data definition of the data in 41,
This data definition differs from the data definition for bit-parallel word-serial data in adapters 10 and 11. Therefore, data conversion devices 20 and 21 need to convert both data format and data definition.

Referring again to FIG. 1, the switching circuit 4 first connects the adapter 1
Word WWt supplied from 0 - Bit parallel word Serial data is received as many times as the number of serial words and supplied to data storage circuit 1, each time bit parallel data from adapter 10 The word specified by PDI word WW Store in position.

The address storage circuit 2 converts the address information specifying the bit position and word position of the data storage circuit 1 into bit permutations of the bit serial data SD by the number of bits of the bit serial data 8D- to be finally output. The bit serial data 8 is written in advance and consists of a read-only memory, etc.@register 3 so that
Address information specifying the first bit position of D is initially set.

When the above-mentioned storage of the bit parallel data PD in the data storage circuit l is completed, the switching circuit 4 operates to input the word RWt-receiving held by the register 3 and supply it to the data storage circuit l. From data storage circuit l, this word RW
The Yoshii poison bit parallel data of the word depth 1 specified by the user is read out to the selection circuit 5, but among the bits of this bit parallel data, the bit RB held by the register 3
Only one bit specified by the selection circuit 5 is selected by the selection circuit 5 and output to the shift register 40.

The word RW and bit RB held by the register 3 are also supplied to the address storage circuit 2.
It is used as address RA (=RW+RB) for reading the next address information from register-3.

FIG. 3 is a diagram for explaining the operation of this embodiment in more detail. If the address information register "6" is initially set in the register 3, the ascending order of the addresses input from the adapter 10 Data definition “ABCDEFGHJt-bit parallel word serial data PD to data definition rGcHA
According to the present invention, it is found that bit serial data 8D having FDBEj can be output by changing the data definition in the log 2 module in the bit parallel processing device. By adopting the above-described configuration for converting bit serial data with different definitions, the program for changing the data definition can be made unnecessary, thereby simplifying the program and improving system processing speed. I can do it.

[Brief explanation of the drawing]

FIG. 1 is an embodiment of the present invention, the second factor is an application example of this embodiment, and FIG. 3 is a diagram for explaining this embodiment. In the figure, 1... data storage circuit, 2...
...Address storage circuit, 3...Register, 4
...Switching circuit, 5...Selection circuit, 10, 11
...adapter, ridges 20, 21 ...data conversion circuit, 30.31 ...maintenance panel, 40.41
...Shift register, 50.51...
Logical device, 60, 61, 70.71... Connection line, 10
0...Data communication line, 200.201, 3
00...Interface line, WW, RW...
・Word, RB...Bit, R person...Address, PD...Bit parallel word serial data, S
D...Bit serial data. Agent: Patent Attorney Oto Uchihara 1. Figure 1 Figure 2 γT'res Data head 1 is the content of the circuit
Write down the huge U article's guest OA'
5 1 B
42 C7 3D 14
E 65
F
36 G
27 H○ Figure 3

Claims (1)

[Claims] In a data conversion method that converts input bit-parallel word-serial data into bit-serial data and outputs the bit-by-bit data, a data storage means for storing the bit-parallel word-serial data and a four-bit order of the bit-serial data are specified. address information storage means pre-stored with address information for the data storage means; and a register holding the address information read out from the address information storage means after the bit-parallel word serial data is stored in the data storage means. The address information read out to the register is used as the next address information reading address from the address information storage means, and the address information read out to the register is used as the next address information read address from the data storage means based on the address information held in the register. A data conversion method characterized in that the bit serial data is output by reading bits one by one.