JPS5897740A - Data converting system - Google Patents

Abstract

PURPOSE:To eliminate a program for alteration of data definition to simplify the program and to increase the system processing speed, by altering the data definition by means of a program of a bit parallel processor. CONSTITUTION:A data storing means 1 stores the bit series data SD which underwent a conversion, and an address information storing means 2 stores the address information which designates the storing position of the means 1. A register 3 holds the address information. In this case, the address information WA which is read out to the register 3 is used for a reading address of the next address information given from the means 2. Then the information is written to the means 2 by one bit and on the basis of the address information which is held at the register 3. Thus the means 2 is read to deliver the bit parallel word series data PD after the bit series data is stored.

Description

[Detailed description of the invention] The present invention relates to a data conversion method.

Bit-parallel word-serial data with a two-dimensional structure in which each digit (bit) constituting a word is processed in parallel and the word is processed serially multiple times is extremely common in the information processing field. It is a data format. On the other hand, each bit that makes up the data.

Bit serial data with a one-dimensional structure in which bits are processed serially one by one is data that is adopted for the purpose of reducing the number of interface lines that carry data, such as data on a data communication line. It is a form.

Equipment for processing bit-serial data t MA for processing bit-parallel word-serial data! For example, when connecting to
If it is necessary to perform data processing in a bit-parallel word-serial data format after data processing in a bit-serial data format, it becomes necessary to convert the bin-to-bit serial data into bit-parallel word-serial data.

A conventional data conversion method of this type uses a shift register tc.
After inputting one bit at a time several times to form a word, the operation of transferring one word held by the shift register to a bit parallel processing device that processes bit parallel word serial data is repeated several times.

By the way, there are cases where the data definition, that is, the order of the bit arrangement, does not match between the shift register and the bit parallel escape device. For example, in a shift register, depending on the convenience of the hardware configuration of the device connected to the shift register other than the bit parallel processing device, the control information and the data controlled by the control information form multiple groups and -The bit array is such that two types of groups are mixed together, whereas in a bit parallel processing device, the bit array is such that the two types of groups are concentrated. There are many cases.

In such cases, in conventional data conversion methods, the bit-parallel word serial data, which is input to the bit-parallel processing device as it is as defined in the shift register, is converted by a program into the data definition in the bit-parallel processing device. This has the disadvantage of complicating the program and slowing down the system processing speed.

An object of the present invention is to provide a data conversion method that simplifies programs and improves system processing speed.

The method of the present invention is a data conversion method for converting input serial data into bit-parallel word serial data and outputting the data, comprising: data storage means for storing the serial data after the conversion;

address information storage means pre-stored with address information for specifying a storage position of the serial data;
a register for holding the address information read from the address information storage means when the bit serial data is stored in the data storage means; The next address information can also be used as an address for reading information (by writing l bit and g to the data storage means based on the address information held in the register) after storing the bit serial data. , the data storage means is read out to output the bit-parallel word-serial data.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows an application example of this embodiment.

Referring to FIG. 1, this embodiment includes a data storage circuit 1 as a data storage means, an address storage circuit 2 as an address information storage means, a register 3, a switching circuit 4, a selection circuit 5, It includes a shift register 40 and an adapter 10 which is a -bit parallel processing device.

Referring to Figure 2, this application example uses two logical devices 50
, 51, two shift registers 40.41, two maintenance panels 30.31, and two data conversion devices 20.21.
, two adapters 10.11, and four sets of connection wires 71,
70, 61.60 and three interface lines 300,
201 and 200, and a data communication line 100.

The logic devices 50 and 51 are configured to send internal signals of the logic devices 50 and 51 to the maintenance panels 3o and 31, respectively, via shift registers 40 and 41, connection lines 7° and 71, and 60 and 61, respectively. . Logic device 50, shift register 4o and connecting wire 60,
70, 61 and 71 can be short and many,
These connection lines transfer multiple bits in parallel.

Normally, in this way, the logic devices 50 and 51 send internal signals for maintenance to the maintenance panels 30 and 31, respectively, but it is also possible to send internal signals to a remote location via the data communication line 100t. With the spread of information processing through data communications, remote maintenance is becoming more and more popular.

Shift register 4 from Ronshio Sousetsu 50 or 51 respectively
Internal signals sent to the adapter 1o or 11 via the adapter 1o or 41 and the data conversion device 20 or 21, respectively, are transmitted to the terminal device at a remote location connected via the data communication line 100 to the maintenance panel. It is converted in adapter 10 or 11 into an internal signal similar to the internal signal supplied to 30 or 31, but this conversion process is performed bit-parallel. Between the adapters 10 and 11, the interface line 300 is installed in a bit-series storage, data room or user's workplace.
1 is designed to carry data communication times [1100 and column data].

Data conversion devices 2o and 21 operate to convert bit-serial data on interface lines 200 and 201, respectively, into bit-parallel word-serial data l at adapters 1o and 11, respectively.

However, the data definition of the bit serial data on the interfaces 1200 and 201 is the shift register 4, respectively.
0 and 41, but this data definition differs from the data definition for bit-parallel word-serial data in adapters 10 and 11.

Therefore, data converters 20 and 21 must convert both data formats and data definitions.

Referring again to FIG. 1, the address storage circuit 2 stores the address information specifying the bit position and word position of the data storage circuit 1 as many times as the number of bits of the bit serial data SD input from the shift register 4°. It is written in advance so as to have the bit permutation of the bit-parallel word-serial data FD that is desired to be output, and is constituted by, for example, a memory dedicated to extraction.

The register 3 is initially set with address information to store the first bit 1 of the bit serial data SD.

The switching circuit 4 first accepts the word WW of the address information held by the register 3 and supplies it to the data storage circuit 1, and the selection circuit 5 selects the word WW of the address information held by the register 3. Supply to circuit 1. One bit of the bit serial data SD sent from the shift register 40 is stored in the position of the data storage circuit 1 specified by the word WW and the bit WB.

The word WW and bit WB held by the register 3 are also supplied to the address storage circuit 2.
It is used as the address WA (=WW+WB) for reading out the next address information from the register 3 to the next address information register 3.

In this way, after reading the bits of the address storage circuit 2t-bit serial data 8D several times and storing them in the bit-serial data 8Di data storage circuit 1, the switching circuit 4 switches the word RWt-receiver supplied from the adapter 10 to It operates to supply the data to the data storage circuit l. From the data storage circuit 1, one word of the bit-parallel word-serial data FD is read out to the bit-parallel processing device from the word position specified by the word RW.

FIG. 3 is a ninth diagram explaining the operation of this embodiment in more detail. If register 3 is initially set to address information [6I, data definition rGcHAFDBEJt input from shift register 40] It can be seen that bit-parallel word serial data PDt- having the data definition ABcDEFGHJ can be output from the serial data.

According to the present invention, bit-serial data is converted into bit-parallel word-serial data with a different data definition by changing the data definition [by a program in a rabbit parallel processing device]. By adopting this configuration, it is possible to eliminate the need for the data definition change program, simplify the ninth program, and improve system processing speed.

[Brief explanation of the drawing]

FIG. 1 is an embodiment of the present invention, FIG. 2 is an application example of this embodiment, and FIG. 3 is a diagram for explaining this embodiment. In the figure, 1...Data storage circuit, 2...Address storage circuit, 3...Register, 4...
Switching circuit, 5... Selection circuit, 10.11...
...Adapter, 20.21...Data converter, 30.31...Maintenance panel, 40°41...
...Shift register, 50.51...Logic device, 60,61,70.71...Connection line, 10
0... Data communication line, 200, 201, 30
0...Interface line, WW, RW...
...Word, WB...Bit, W person...
・Address, PD...Bit parallel word serial data, 8D...Bit serial Figure 1 Figure 2 Address data t and ・1102 each r gradient Address □ Address note (・Breathing rotation number r content OA 5 1 B
42 C7 3D 14
E 6 S F
36 (r
27 HQ Figure 3

Claims (1)

[Claims] In a data conversion method for converting input bit-serial data into bit-parallel word-serial data and outputting the converted bit-serial data, a data storage means for storing the converted bit-serial data and a means for specifying a storage position of the bit-serial data are provided. An address information storage means in which address information is stored in advance, and a register that holds the address information read out from the address information storage means when the bit serial data is stored in the data storage means, and The output address information is used as an address for reading the next address information from the address information storage means, and one bit at a time is sent to the data storage means based on the address information held in the register. A data conversion method characterized in that after storing the bit-serial data by writing, the data storage means is read out to output the bit-parallel word-serial data.