JPS5895452A - Controlling system for demodulation carrier phase - Google Patents

Controlling system for demodulation carrier phase

Info

Publication number
JPS5895452A
JPS5895452A JP19417381A JP19417381A JPS5895452A JP S5895452 A JPS5895452 A JP S5895452A JP 19417381 A JP19417381 A JP 19417381A JP 19417381 A JP19417381 A JP 19417381A JP S5895452 A JPS5895452 A JP S5895452A
Authority
JP
Japan
Prior art keywords
signal
phase
error
demodulation
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19417381A
Other languages
Japanese (ja)
Inventor
Yoshiaki Tanabe
田辺 義昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP19417381A priority Critical patent/JPS5895452A/en
Publication of JPS5895452A publication Critical patent/JPS5895452A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/49Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/497Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To correct the group delay distortion in a demodulating circuit, by controlling a demodulation carrier by a phase error, which is obtained from the difference between a demodulated impulse response and a reference level, in the demodulation of the transmission system using the class IV (10-1) partial response encoding. CONSTITUTION:A demodulation signal which is obtained from an input terminal and is converted to a class IV partial response code is sent to a pattern detector 1, which detect pattern (+ or -1, 0, + or -1), and an error detector 2 which operates the difference between the demodulation signal and a reference level signal 12 to detect the polarity of phase error information as an error signal. A storing equipment 3 stores this error signal, and the error signal is sent to an integrator 4 only when a signal is outputted from the pattern detector 1. The phase of the demodulation carrier is controlled by a control voltage 13 from the integrator 4. Thus, the waveform distortion due to the group delay distortion of a transmission line is corrected.

Description

【発明の詳細な説明】 本発明はクラス(class)  I V 3値ノく−
シャルレスポンス符号化された受信ペースノ(ンド信号
の復調キャリア位相制御方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to class I V ternary
This invention relates to a demodulation carrier phase control system for a received pace signal encoded by a digital signal.

一般に、データ信号等の波形伝送において、復調キャリ
アの位相によって復調信号(以下、受信信号と称する)
の波形が変化することは良く知られているが、伝送路に
おいて振幅歪や群遅延歪が発生しない場合には、いわゆ
る同期検波(復調)によって波形歪のない信号を復調す
ることが可能である。これに反して伝送路に歪がある場
合、特に群遅延歪のある場合には、前記同期検波の際に
復調キャリアの位相が伺等制限されることなく与えられ
ると、受信信号に対して波形歪が生じ、送信データを正
確に再生することができない。従って従来は、復調キャ
リアの位相を手動によって適当に調整することによって
、受信信号の波形歪を軽減することもあるが、伝送路の
切替え等によつて特性が変化する度に再調整せねばなら
ないという欠点があった。
Generally, in waveform transmission of data signals, etc., the demodulated signal (hereinafter referred to as received signal) is determined by the phase of the demodulated carrier.
It is well known that the waveform of a signal changes, but if amplitude distortion or group delay distortion does not occur in the transmission path, it is possible to demodulate a signal without waveform distortion by so-called synchronous detection (demodulation). . On the other hand, if there is distortion in the transmission path, especially if there is group delay distortion, if the phase of the demodulated carrier is given without any restrictions, such as during the synchronous detection, the waveform will change with respect to the received signal. Distortion occurs and the transmitted data cannot be reproduced accurately. Therefore, conventionally, the waveform distortion of the received signal can be reduced by manually adjusting the phase of the demodulated carrier appropriately, but this must be readjusted every time the characteristics change due to switching of the transmission path, etc. There was a drawback.

本発明の目的は、上記の欠点を除去し、伝送路の切替え
や特性の変動によるも、伝送路において波形歪をともな
って受けられる受信信号を復調器の出力側に歪なく補正
復調することのできる構成の簡単な復調キャリア位相制
御方式を提供するにある。
An object of the present invention is to eliminate the above-mentioned drawbacks, and to correct and demodulate the received signal, which is received with waveform distortion on the transmission line, without distortion, to the output side of the demodulator, even if the transmission line is switched or the characteristics change. The object of the present invention is to provide a demodulation carrier phase control system with a simple configuration.

本発明によれば、変調して送出されるクラスI■3値パ
ーシャルレスポンス符号化されタテータ信号を伝送路を
介して受信復調するデータ信号による波形伝送方式にお
いて、受信信号の(+1 、0 。
According to the present invention, in a waveform transmission method using a data signal in which a modulated and transmitted Class I ■ ternary partial response encoded tatator signal is received and demodulated via a transmission path, (+1, 0) of a received signal.

−1)又は(−1,0,+1)のパターンを検出するパ
ターン検出器と、前記受信信号と基準レベル信号とで誤
差を検出する誤差検出器と、前記パターン検出器が前記
パターンすなわち(+1 、0 、−1 )又は(−1
、0、+1 )を検出したどきのみ前記誤差検出の出力
を入力とする積分器とを具え、前記記憶された誤差信号
を前記積分器にて積分平滑し、極性が正の場合は復調キ
ャリアの位相を(下側波帯変調の場合は)遅らせ、(上
側波帯変調の場合は)進ませ、極性が負の場合は復調キ
ャリアの位相を(下側波帯変調の場合は)進ませ、(上
側波帯変調の場合は)遅らせる制御を行なうことを判徴
とする復調キャリア位相制御方式が得られる。
-1) or (-1, 0, +1); an error detector that detects an error between the received signal and the reference level signal; , 0 , -1 ) or (-1
, 0, +1), the stored error signal is integrated and smoothed by the integrator, and when the polarity is positive, retards the phase (for lower sideband modulation), advances (for upper sideband modulation), advances the phase of the demodulated carrier (for lower sideband modulation) if the polarity is negative, (In the case of upper sideband modulation) A demodulation carrier phase control method characterized by performing delay control is obtained.

次に本発明による復調キャリア位相制御方式の実施例に
ついて図面を参照して説明する。
Next, an embodiment of the demodulation carrier phase control method according to the present invention will be described with reference to the drawings.

一般にクラスIVa値パーシャルレスポンス符号化のデ
ータ信号において、伝送路に歪がない状態で同期検波を
行なった場合のインパルス応答を第1図に、伝送路であ
る傾斜(仮に正の傾斜と称す)の群遅延歪を生じた状態
で復調キャリアの位相を調整することなく同期検波を行
なった場合のインパルス応答を第2図に、および伝送路
で前記とは逆の傾斜(仮に負の傾斜と称す)の群遅延歪
を生じた状態で復調キャリアの位相を調整することなく
同期検波を行なった場合のインパルス応答を第3図に示
す。ただし、これらの図において周期Tは送信部の系が
帯域幅Bで制限されていると仮定した場合、T=1/2
B と表わされる、第1図の伝送路無歪、同期検波の状
態から復調キャリアの位相をずらすと、位相を進めた場
合は第2図のインパルス応答となり、逆に位相を遅らせ
ると第3図のようなインパルス応答となる。従って、正
の傾斜の群遅延歪を有する場合、復調キャリアの位相を
遅らせて行くと第1図のようなインパルス応答に近づけ
ることのできる最適な復調キャリアの位相が存在し、逆
に負の傾斜の群遅延歪を有する伝送路の場合、復調キャ
リアの位相を進めていくと、同様に第1図のインパルス
応答に近づけることのできる最適位相が存在する。
Figure 1 shows the impulse response when synchronous detection is performed on a class IVa value partial response encoded data signal with no distortion in the transmission path. Figure 2 shows the impulse response when synchronous detection is performed without adjusting the phase of the demodulated carrier in a state where group delay distortion occurs, and the slope opposite to the above (temporarily referred to as negative slope) in the transmission path. FIG. 3 shows an impulse response when synchronous detection is performed without adjusting the phase of the demodulated carrier in a state where group delay distortion of . However, in these figures, assuming that the transmitter system is limited by the bandwidth B, the period T is T = 1/2
If we shift the phase of the demodulated carrier from the transmission line distortion-free, synchronous detection state shown in Figure 1, which is expressed as The impulse response is as follows. Therefore, when the group delay distortion has a positive slope, there is an optimal demodulated carrier phase that can be approximated to the impulse response shown in Figure 1 by delaying the phase of the demodulated carrier; In the case of a transmission line having a group delay distortion of , as the phase of the demodulated carrier is advanced, there exists an optimum phase that can similarly approach the impulse response shown in FIG. 1.

第4図は本発明の動作波形図で、第4図のaは第3図の
インパルス応答、bは第1図のインパルス応答Cの基準
電圧、dは位相誤差情報である。。
FIG. 4 is an operational waveform diagram of the present invention, where a in FIG. 4 is the impulse response in FIG. 3, b is the reference voltage of the impulse response C in FIG. 1, and d is phase error information. .

第4図において、aのインパルス応答はdの位相誤差情
報を積分平滑することによシaのインパルス応答に近づ
けることによりインパルス応答は最良の状態に補正され
たことになり、ここで復調キャリアの位相調整を停止す
るようにすればよい。
In Fig. 4, the impulse response of a is brought close to the impulse response of shea a by integrating and smoothing the phase error information of d, and the impulse response is corrected to the best condition. What is necessary is to stop the phase adjustment.

又、第2図のインパルスの応答の場合でも位相の補正方
向のみ前記とは逆で動作は同じである。
Also, in the case of the impulse response shown in FIG. 2, the operation is the same except that the direction of phase correction is opposite to that described above.

次に本発明の実施例を第5図にて説明する。入力端子1
1から供給されたクラスIVa値パーシャルレスポンス
符号化された受信信号は、3ビツトのシフトレジスタを
具え、(+1 、 O、−1) 、 (−1゜0、+1
)のパターンを検出するパターン検出器1と、前記受信
信号と基準レベル信号12との差をとることによ多位相
誤差情報の極性をvt差化号として検出する誤差検出器
とへ送られる。記憶@3はこの誤差信号を記憶し、パタ
ーン検出器2にて(+1 、 O、−1)又は(−1,
0,+1)のパターンを検出したときのみ記憶された誤
差信号を私分器4へ送出し、積分器4で積分平滑されて
得られる制御電圧13によって、その極性が正の場合ね
、復調キャリアが最適位相なるように位相を遅らせ、極
性が負の場合は’ff1Eキャリアが最適位相となるよ
うに位相を進ませることにより、伝送路の群遅延歪等に
よって生じた受信信号の波形歪は補正される。
Next, an embodiment of the present invention will be described with reference to FIG. Input terminal 1
The class IVa value partial response encoded received signal supplied from 1 is provided with a 3-bit shift register, (+1, O, -1), (-1°0, +1
), and an error detector that detects the polarity of the multiphase error information as a vt difference signal by taking the difference between the received signal and the reference level signal 12. Memory @3 stores this error signal, and the pattern detector 2 detects (+1, O, -1) or (-1,
0, +1) is detected, the stored error signal is sent to the private divider 4, and is integrated and smoothed by the integrator 4, and the control voltage 13 obtained is used to detect the demodulated carrier if the polarity is positive. Waveform distortion of the received signal caused by group delay distortion of the transmission path can be corrected by delaying the phase so that the 'ff1E carrier has the optimal phase and advancing the phase so that the 'ff1E carrier has the optimal phase if the polarity is negative. be done.

以上の説明によって明らかなように、本発明によれば、
自動等什器のような高価な補正機能を備えることなく、
簡単な回路構成で伝送路の群遅延歪によって生ずる受信
信号の波形歪を伝送路の特性の変仕に対しても適応して
補正すべく自動的に動作させることができ、これによっ
て伝送システムにおl−Jる侶チの品質向上に対しても
大きな効果が得られる。
As is clear from the above description, according to the present invention,
Without the need for expensive correction functions like automatic fixtures,
With a simple circuit configuration, the waveform distortion of the received signal caused by the group delay distortion of the transmission line can be automatically corrected by adapting to variations in the characteristics of the transmission line. A great effect can also be obtained in improving the quality of the food.

【図面の簡単な説明】[Brief explanation of drawings]

ゴミ1図、食も2図、剪」3し」は一般のクラスIVa
値パーシャルレスポンス+f−Q化のデータ信号の一同
期検波比力會示す波形1、第4図は本発明の原理を散開
するだめの波形図、第5ν1は本発明の実施例の主要部
を示すブロック図である。 1・・・・・・パターン検出器、2・・・・・・を差校
・出器、3・・・・・・記憶ヒ1.4・・・・・・わ1
分器、11・・・・・入力端子、12・・・・・・基紙
レベル信号、13・・・・・・制御電圧。 番 l 図 手2 図 拳3 薗
Garbage is 1, food is 2, and cutting is 3. General class IVa.
Waveform 1 shows the synchronized detection ratio of the data signal of value partial response + f-Q conversion, Figure 4 is a waveform diagram for expanding the principle of the present invention, and Figure 5v1 shows the main part of the embodiment of the present invention. It is a block diagram. 1... Pattern detector, 2... Differential/output device, 3... Memory Hi 1.4... Wa 1
Divider, 11...Input terminal, 12...Base level signal, 13...Control voltage. Number l Zute 2 Zuken 3 Sono

Claims (1)

【特許請求の範囲】 クラスIVB値パーシャルレスポンス符号化すれた受信
信号から(+1 、0−、−1 ) 、 (−1、O、
+1 )のパターンを検出するパターン検出器と、前記
受信信号と基準レベル信号との位相差の極性を示す誤差
信号を得る誤差検出器と、前記誤差信号を記憶し前記パ
ターン検出器が前記(+1.0.−1)。 (−1,0,+1)のパターンを検出したときのみ記憶
された前記誤差信号を出力する記憶器と、前記記憶器の
出力を積分平滑し、その極性が正の場合は復調キャリア
の位相を下側波帯変調の場合は遅らせ、上側波帯変調の
場合は進ませ、極性が負の場合は復調キャリーアの位相
を下側波帯変調の場合は進ませ、上側波帯変調の場合は
遅らせる制御を行なう制御信号を出力する積分器とを具
えることを特徴とする復調キャリア位相制御方式。
[Claims] From the received signal encoded with class IVB value partial response (+1, 0-, -1), (-1, O,
a pattern detector that detects the pattern of (+1); an error detector that obtains an error signal indicating the polarity of the phase difference between the received signal and the reference level signal; and an error detector that stores the error signal and detects the pattern of (+1). .0.-1). A memory device outputs the error signal stored only when a pattern of (-1, 0, +1) is detected, and the output of the memory device is integrated and smoothed, and if the polarity is positive, the phase of the demodulated carrier is changed. Delays for lower sideband modulation, advances for upper sideband modulation, and advances the phase of the demodulated carrier if the polarity is negative for lower sideband modulation and retards for upper sideband modulation A demodulation carrier phase control method characterized by comprising an integrator that outputs a control signal for controlling.
JP19417381A 1981-12-02 1981-12-02 Controlling system for demodulation carrier phase Pending JPS5895452A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19417381A JPS5895452A (en) 1981-12-02 1981-12-02 Controlling system for demodulation carrier phase

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19417381A JPS5895452A (en) 1981-12-02 1981-12-02 Controlling system for demodulation carrier phase

Publications (1)

Publication Number Publication Date
JPS5895452A true JPS5895452A (en) 1983-06-07

Family

ID=16320136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19417381A Pending JPS5895452A (en) 1981-12-02 1981-12-02 Controlling system for demodulation carrier phase

Country Status (1)

Country Link
JP (1) JPS5895452A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5696793A (en) * 1994-11-11 1997-12-09 Fujitsu Limited Phase difference detection circuit for extended partial-response class-4 signaling system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5696793A (en) * 1994-11-11 1997-12-09 Fujitsu Limited Phase difference detection circuit for extended partial-response class-4 signaling system

Similar Documents

Publication Publication Date Title
JPH021675A (en) Carrier recovering circuit for offset qpsk system
CA1157112A (en) Quadriphase differential demodulator
JPS58130658A (en) Modulator/demodulator set for digital communication
JPH06132994A (en) Timing extracting device
US5949829A (en) Central error detecting circuit for FSK receiver
JPS5895452A (en) Controlling system for demodulation carrier phase
US4807251A (en) PSK modem system with improved demodulation reliability
JPH0428185B2 (en)
CA2318759A1 (en) Digital demodulator
JPS5975742A (en) Phase control system of demodulated carrier
JP2522398B2 (en) Phase control device
JPH05211526A (en) Dc center level automatic correction circuit for base band signal
SU1381684A1 (en) Synchronous demodulator
JPS60145753A (en) Demodulator
JPH03201643A (en) Demodulation carrier phase control system
JPH05236044A (en) Automatic level controller
JPS62159543A (en) Timing synchronizing detection circuit of digital reception equipment
JPS62159559A (en) Demodulator control system
JPS6028457B2 (en) clock regeneration circuit
JPS59128853A (en) Preamble detector
JPH05327786A (en) Ternary signal transmission system using optical transmission pulse
JPH0993041A (en) Envelope detection circuit
JPH03145843A (en) Tank limiter system inverse modulation type demodulation circuit
JPH02172322A (en) Sampling clock regenerating device
JPS61136350A (en) Carrier wave recovery circuit