JPS60145753A - Demodulator - Google Patents

Abstract

PURPOSE:To correct automatically the change in group delay distortion of a transmission line by allowing a signal detection circuit detecting the presence of a reception signal to control a switch circuit and a both switches connecting or opening an output of integration. CONSTITUTION:A reception signal fed from an input terminal 1 is fed to a pattern detector 4 detecting a pattern, an error detector 5 detecting the polarity of phase error information as an error signal and a signal detector 6 detecting the presence of a reception signal. A storage device 7 stores an error signal from the error detector 5, a pattern detector 4 uses the error signal stored only when a specific pattern is detected as the 1st input to a switch 8, its output is fed to a 1st integration device 9 and smoothed. One output of the integration device 9 is given to the 1st input of a switch 12 and the other is given to a switch circuit 10. This output is fed to a 2nd integration device 11 holding the output of the integration device 9. With the output of the signal detector 6, that is, the presence of the signal, the output of the 1st integration device 9 or the 2nd integration device 11 is outputted from a terminal 3 by the switch 12.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a demodulation device that demodulates a class ■ ternary partial response encoded data signal that is modulated and transmitted via a transmission path. be.

[Prior art]

It is generally well known that in waveform transmission of data signals and the like, the waveform of the demodulated signal changes depending on the demodulated carrier phase. If amplitude distortion or group delay distortion does not occur in the transmission path, so-called synchronous detection (demodulation)
It is possible to demodulate a signal without waveform distortion. On the other hand, when there is distortion in the transmission path, especially when there is group delay distortion, if the phase of the demodulated carrier is given without any restriction during the above-mentioned coherent detection and is always constant,
Waveform distortion occurs in the received signal, resulting in the inconvenience that the transmitted data cannot be accurately reproduced.

Therefore, conventional methods have been used to reduce the waveform distortion of the received signal by manually adjusting the phase of the demodulated carrier.

However, such means have the disadvantage that readjustment is required each time the characteristics change due to switching of the transmission path or the like.

[Object and structure of the invention]

In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks, and its purpose is to adapt to changes in group delay distortion of a transmission line with a simple circuit configuration. To provide a demodulator that can automatically correct the signal, stably shorten the time required for control, and quickly perform corrective demodulation without distorting the output of the received signal. .

In order to achieve such an objective, the present invention provides class III
From the value partial response encoded received signal (+
1.0. -1) +(-1, t), +1); a pattern detector for detecting a specific pattern; an error detector for obtaining an error signal indicating the polarity of the phase difference between the received signal and the reference level signal; A signal detector that detects the presence or absence of a signal; a memory that outputs the error signal only when the pattern detector detects a specific pattern; and a memory that outputs the error signal only when the pattern detector detects a specific pattern. A first switch selects and outputs the output, and the output of this first switch is integrated and smoothed, and when the polarity is positive, the phase of the demodulated carrier is delayed during lower sideband modulation and advances during upper sideband modulation. a first integrator that produces a control signal that advances the phase of the demodulated carrier during lower sideband modulation and retards it during upper sideband modulation when the polarity is negative; and an output of the first integrator. a switch circuit to connect or open; a second integrator that integrates and smooths the output of the switch circuit and holds the output and uses the output as a second input of the first switch; The output of the second integrator is used as a first input, and the output of the second integrator is used as a second input to select and output one of these two manually. The first and second switching devices and the switch circuit are controlled.

1 Embodiment] Hereinafter, an embodiment of the present invention will be described in detail based on the drawings.
l Figures J, 2 and 3 are waveform diagrams showing the synchronous detection output of a data signal of general class 1 ternary partial response encoding. In order to make the present invention easier to understand, this will be explained first.

Figure 1 shows the impulse response when synchronous detection is performed with no distortion in the transmission path for data signals of class ■ three-level partial response encoding. ) Figure 2 shows the impulse response when synchronous detection is performed without adjusting the phase of the demodulated carrier in a state where group delay distortion occurs. FIG. 3 shows an impulse response when synchronous detection is performed without adjusting the phase of the demodulated carrier in a state where the group delay distortion (referred to as 1) has occurred.

However, in each of these figures, if it is assumed that the transmitter system (not shown) is limited by the bandwidth B, the frequency 101T is expressed as T=1/2B.

If the phase of the demodulated carrier is shifted from the transmission line distortion-free, synchronous detection state shown in Figure 1, if the phase is advanced, the second
The impulse response shown in the figure is obtained, and conversely, if the phase is delayed, the third
The impulse response is shown in the figure.

Therefore, in the case of a transmission line with a group delay distortion with a positive slope, the phase of the demodulated carrier exists, and conversely, in the case of a transmission line with a group delay distortion with a negative slope, when the phase of the demodulated carrier is advanced, Similarly, there is an optimal phase that can be approximated to the impulse response of FIG.

FIG. 4 is a waveform diagram for detailed explanation of the present invention, where a shows the impulse response of FIG. 3, and b shows the first impulse response.
The impulse response shown in the figure is shown. Further, C indicates a reference voltage, and d indicates phase error information.

In this FIG. 4, the impulse response a is the phase error part i
By integrating and smoothing d to bring it closer to the impulse response, the impulse response has been corrected to the best condition, and the adjustment of the demodulated carrier phase is now completed.

Also, at this time, even if the received signal is disconnected, the demodulated carrier
The a phase does not run free, but is controlled by the control signal that maintains the optimal phase, and when the received signal is demodulated again, the phase starts to be controlled by the control signal that maintains the optimal phase, so demodulation occurs quickly. Stop carrier phase pressure adjustment. Further, even in the case of the impulse response shown in FIG. 2, the operation is the same except that only the phase correction direction is reversed.

Now, the present invention is implemented as follows.

FIG. 5 is a block diagram showing an embodiment of a demodulating device according to the present invention, and only the parts necessary for explanation are shown.

In FIG. 5, 1 is an input terminal to which the received 1δ signal encoded by the class ■ ternary partial resbo/s is supplied;
2 is an input terminal to which a reference level signal is supplied, and 3 is an output terminal from which a demodulated signal 1, which is a control signal, is obtained.

Then, 4 is a 3-bit register km, and the received signal supplied from input terminal 1 is (+l, L), l) + (-1, Ll).
, +1) a pattern detector for detecting a specific pattern of 5
6 is an error detector that obtains an error signal indicating the polarity of the phase difference between the received signal and the reference level signal supplied from input terminal 2; 6 is a signal detector that detects the presence or absence of the received signal from input terminal 1; γ; 8 is a memory which receives the output of the pattern detector 4 and the output of the error detector 5 and outputs an error signal from the error detector 5 only when the pattern detector 4 detects a specific pattern; This is a first switch which selects and outputs one of these two manual inputs, with the output from the second integrator as the first input and the output from the second integrator, which will be described later, as the second input.

9 integrates and smooths the output of this first switch 8, and if the polarity is positive, the phase of the demodulated carrier is delayed to the lower sideband modulation and advances to the upper sideband modulation; A first integrator that produces a control signal that advances the phase of the demodulated carrier during lower sideband modulation and retards it during upper sideband modulation in the case of a negative value; 10 connects or opens the output of this first integrator 9; 11 is a second integrator that integrates, smoothes and holds the output of the switch circuit 10; 12 is a second integrator 11 whose first input is the output of the first integrator 9;
This is a second switching device which takes the output of the input as the second input and selects one of these two manual inputs and outputs it.

Then, as shown by the broken line, the output of the signal detector 6 causes the first and second switching devices 8, 12 and the switch circuit 1 to be connected to each other.
0.

Next, the operation of the embodiment shown in FIG. 5 will be explained.

First, the class ■ ternary partial response encoded received signal supplied from input terminal 1 is provided with a 3-bit register, (+1.(11-1)+(-1°0, +1
), an error detector 5 that detects the polarity of the phase error information as an error signal by taking the difference between the received signal and the reference level signal supplied from the input terminal 2, and a receiver. The signal is sent to a signal detector 6 that detects the presence or absence of a signal.

Then, the memory T stores the error signal from the error detector 5, and the pattern detector 4 (+l, 11.-1)+(-
The error signal stored only when a specific pattern of 1. 9
The first integrator 9 integrates and smooths the signal. The output of this first integrator 9 is branched into two directions;
A switch circuit 1 that is given to the first input of a second switch 12 that outputs one side from human power and connects or opens the other side.
Then, the output of this switch circuit 10 is sent to a second integrator 11 that holds the output of the first integrator 9, and the output of this second integrator 11 is branched into two directions. , one is given as a second input to the first switch 8, and the other is given as a second input to the second switch 12.

Next, when the received signal is input normally,
The first switch 8 is controlled by the signal detector 6 and sends the first manual input, that is, the error signal, to the first integrator 9.
The error signal is integrally smoothed. Then, the second switch 12 supplies the first input, that is, the integrated and smoothed error signal, to the output terminal 3 as a demodulation signal which is a control signal, and when the polarity is positive, the phase of the demodulation carrier The phase is delayed so that the phase becomes the optimum phase, and when the polarity is negative, control is performed to advance the demodulated carrier phase.

On the other hand, the switch circuit 10 connects the output of the first integrator 9, that is, the control signal for which the phase of the demodulated carrier becomes the optimum phase, to the second integrator 11. and provides the control signal held as the second input of the first switch 8 and the second switch 12.

Next, when the received signal is cut off, this is detected by the signal detector 6, and the output of the signal detector 6 is used to switch the first switch 8. The switch circuit 10 and the second switch 12 are each controlled, the switch circuit 10 releases the connection between the first integrator 9 and the second integrator 11, and the second switch 12 disconnects the second input , that is, the second integrator 11
The phase of the demodulated carrier is controlled by the control signal held in
The control signal held by the second integrator 11 is given to the first integrator 9.

Then, when the received signal is restored again, the control signal held by the first integrator 9 starts to control the phase of the demodulated carrier.

In this way, when the received signal is input normally, the first switch 8 outputs the first input, i.e., the output of the memory 7, under the control of the signal detector 6. The phase of the demodulated carrier is controlled by the second switch 12, and the other is applied to the second integrator 11 via the switch circuit 10. to hold the output of the first integrator. When the received signal is disconnected, the switch circuit 10 controlled by the output of the signal detector 6 opens the connection between the output of the first integrator 9 and the second integrator 11, and Switcher 12
The phase of the demodulated carrier is maintained by the output of the second integrator 11 at its second input, and the first switch 8
The output of the second integrator 12, which is the input of
is given to hold the output of the first integrator 9. Then, when the received signal is restored, the control signal held in the first integrator 9 starts to control the phase of the demodulated carrier.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a memory device that receives the output of a pattern generator and an output of an error detector as input, and a signal that detects the presence or absence of a demodulated signal, can be used without using complicated means. a detector; a first switch that receives the output of the memory and the output of the second integrator and selects and outputs either one; a first switch that integrates and smoothes the output of the first switch;
an integrator, a switch circuit that connects or disconnects the output of the first integrator, a second integrator that integrates and smooths the output of the switch circuit and maintains it, and the first and second integrators. A simple circuit configuration includes a second switch that receives the output of the signal detector as input and selects and outputs one of the switches, and the first and second switches and the switch circuit are controlled by the output of the signal detector. , it adapts to and automatically compensates for changes in group delay distortion of the transmission path, and the time required for control can be stably shortened, allowing for prompt correction demodulation without distorting the output of the received signal. The practical effects are extremely large, since the quality of the transmission system can be improved.

[Brief explanation of drawings]

Figures 1, 2, and 3 are waveform diagrams showing the synchronous detection output of a data signal of general class ■ ternary partial response encoding, which serves to explain the present invention, and Figure 4 is a detailed diagram of the present invention. FIG. 5 is a block diagram showing an embodiment of a demodulator according to the present invention. 4... Pattern detector, 5... Error detection 11 mounds:
I, 6... Signal detector, 7... Memory device, 8...
・First switch, 9...first integrator, 10...
・Switch circuit, 11... Second integrator, 12...
...Second switch.・Otsu].

Claims (1)

[Claims] Class ■A pattern detector that detects a specific pattern of (+1.tl, -1), (-1, +1.+1) from a ternary partial response encoded received signal, and the position of the received signal and a reference level signal. an error detector that obtains an error signal indicating the polarity of the phase difference; a signal detector that detects the presence or absence of the received signal; and a signal detector that outputs the error signal only when the pattern detector detects a specific pattern. , a first switch that selects and outputs one of the two outputs using the output of this memory as the first input, and a demodulated carrier that integrates and smooths the output of this first switch and when the polarity is positive. a control signal that causes the phase of the demodulated carrier to be delayed during lower sideband modulation and advanced during upper sideband modulation, and when the polarity is negative, the phase of the demodulated carrier is advanced during lower sideband modulation and delayed during upper sideband modulation; a first integrator that produces the output of the first integrator, a switch circuit that connects or opens the output of the first integrator; a second integrator that takes the output of the first integrator as the first input and the output of the second camphor divider as the second input, and selects one of these two manually and outputs it. A demodulating device comprising: a second switch for controlling the signal detector, and configured to control the first and second switches and the switch circuit based on the output of the signal detector.