JP2532418B2 - Automatic ringing removal circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic ringing removal circuit that automatically removes a ringing signal component in a video signal generated in a transmission circuit.

2. Description of the Related Art When transmitting a wideband video signal such as a high-definition television signal, a method of band-compressing the video signal has been studied. As one, the so-called MUSE (Mu ltiple S ubny
quist S ampling E ncoding) system has been proposed. The details of the contents are shown in, for example, "High-definition television satellite 1-channel transmission system (MUSE)" by Yuichi Ninomiya et al., IEICE, Technical Report, IE84-72, 1984.

 FIG. 2 shows an outline of the MUSE system.

On the transmitting side, the video signal obtained by the high-definition camera 21 is converted into an analog-digital conversion circuit (hereinafter referred to as A / D circuit) 2
Converted to digital signal in 2 and subsampling circuit 23
After the sampling process is performed by, the digital-analog conversion circuit (hereinafter referred to as D / A circuit) 24 reconverts the signal into an analog signal, and the FM modulation circuit 25 performs FM modulation for transmission.

On the receiving side, this FM signal is received and input from the input terminal 1 and demodulated into a baseband signal by the FM demodulation circuit 2 and A / D
The circuit 7 modulates the digital video signal. further,
The signal missing due to the sub-sampling processing on the transmitting side is interpolated by the two-dimensional interpolation circuit 17 and reproduced, and the D / A circuit 18
Reconverted to analog video signal by
19 to play the video.

On the other hand, the horizontal synchronizing signal for phase synchronization is added to the video signal with a waveform as shown in FIG. On the receiving side, the horizontal synchronization signal is received, sampled by the sampling clock b, and (level at point ii + ii
The calculation of (i level)-(i level) × 2 is performed. If the output is 0, it is determined that the phase of the sampling clock for reception matches. When the phase of the sampling clock on the reception side is advanced, the operation output becomes positive, and when it is delayed, it becomes negative. Therefore, the operation output is controlled so that the phase shift is determined and the phases are matched.

However, even if the sampling phase is adjusted by using the horizontal synchronizing signal in this way, the sampling position of the video signal may still be displaced and ringing may occur.

For example, in a VTR, the sync signal may be replaced when recording the video signal, but at this time it is very difficult to add the sync signal to the video signal with high accuracy and at the time of playback. The position changes. Therefore, if a sampling clock that matches the horizontal synchronization signal is used, the video signal cannot be sampled correctly. Thus, if the sampling position of the video signal shifts, the output signal of the sub-sampling circuit on the transmission side and the output signal of the A / D circuit on the reception side do not match, and the video signal is output by the two-dimensional interpolation circuit 17 on the reception side. Cannot be reproduced correctly, and ringing occurs in the video signal. Therefore, it is necessary to control the phase of the sampling clock on the receiving side to an optimum phase that minimizes ringing.

FIG. 5 shows how ringing occurs when the sampling clock phase is shifted. FIG. 5A shows the input waveform of the A / D circuit 7 in which the video signal changes from the high level state to the low level state, and FIG. 5B shows the waveform of the sampling clock on the receiving side. I have. When the phase of the sampling clock b is optimum, it is in the state of the solid line, and when the phase of the sampling clock b is ahead of the optimum state, it is shown by the broken line. Considering the actual case, when the waveform of the video signal a is sampled at the rising edge of the sampling clock b (point in FIG. 5a),
The output waveform ideally switches the signal from the high level to the low level as shown by the solid line in FIG. 5c. But,
When the phase of the sampling clock advances, the point x in FIG. 5a is sampled and its output waveform becomes a signal with ringing as shown by the broken line in FIG. 5c. The same applies to the case where the phase of the sampling clock is delayed, which also causes ringing.

FIG. 3 is a block diagram of a conventional circuit for manually adjusting ringing. Briefly, the output signal of the transmitter is input from the input terminal 1, demodulated into a baseband signal by the FM demodulator 2, and deemphasized by the deemphasis circuit 3. Furthermore, the input signal from the external input terminal 5 and the input switching circuit 4 are used for switching, and the band is limited by the LPF 6, then the A / D
The circuit 7 converts the signal into a digital signal.

The phase difference detection circuit 8 outputs the result of the above calculation as a phase error detection output. The adder 9 adds the phase error detection output and the data from the phase addition data adjusting circuit 16 and integrates this output signal by an integrator 10 and then adds it to a voltage controlled oscillator (hereinafter referred to as VCO) 11. . This VCO11
Generates a sampling clock for the A / D circuit 7, and the output signal of the integrator 10 controls this A / D sampling clock phase. Here, the phase addition data adjustment circuit 16
Thus, the phase of the sampling clock of the A / D circuit is controlled by manually varying the data to be added to the adder circuit 9 so that the ringing can be minimized and an optimum video signal can be obtained.

The problem to be solved by the invention However, in the above-described conventional configuration, it is necessary to manually adjust the phase of the sampling clock of the A / D circuit to the optimum point of ringing, which is very troublesome.

The present invention solves this conventional problem and automatically controls the phase of the sampling clock of the A / D circuit when a video signal has ringing to obtain an optimum video signal. The purpose is to provide a removal circuit.

Means for Solving the Problems The present invention relates to an amplifier to which a sub-sampled video signal is input, an A / D circuit which receives an output signal of the amplifier and converts the output signal into a digital signal, and an A / D circuit added to the input video signal. A phase error detection circuit for detecting the phase error of the sampling clock of the A / D circuit by the synchronizing signal,
A means for detecting the ringing amount in the output signal of the D circuit to obtain added data, a means for detecting a fixed level specified on the transmitting side in the input signal, and an output signal of this fixed level detecting means for an analog signal. D / A circuit to convert to this D / A
A means for feeding back the output of the circuit to the amplifier, an adder for adding the phase error detection power and the phase addition data, an integrator for integrating the output signal of this adder, and an A /
It has a VCO for controlling the phase of the sampling clock of the D circuit.

Action The present invention, by the above configuration, feeds back the fixed level amount specified on the transmission side to the amplifier before the A / D circuit is input, and uses the ringing amount detection output as the phase addition data, thereby eliminating any input signal. However, it is possible to automatically control the optimum sampling clock phase so as to obtain the desired amplitude level of the video signal and minimize the ringing amount of the video signal.

Embodiment An embodiment of the present invention will be described below with reference to FIG.

An FM video signal sent from the transmission side is input to the first input terminal 1, and a baseband video signal that is not pre-emphasized is input to the second input terminal 5.
The FM video signal sent from the transmitting side is input to the FM demodulator 2 for FM demodulation, de-emphasis processed by the de-emphasis circuit 3, and then applied to the input switching circuit 4.
The video signal from the input terminal 5 is switched. Then, the signal is amplified by the amplifier 13, band-limited by the LPF 6, and then converted into a digital signal by the A / D circuit 7. This digital signal is input to the fixed level detection circuit 14. The fixed level to be detected here is a signal whose magnitude is defined in the MUSE system signal, for example, the first half (255/25) of the line with the framing pulse shown in FIG.
5 and 0/255) and clamp line level (127/255) …… 5
Lines 567 and 567 can be used. Here when using framing pulse (255/255 and 0/255)
Will be described. The framing pulse has a repeating pulse of 17.5 pairs from high level (255/255) on the 605th line as shown in Fig. 6a, and on the 606th line, Fig. 6b.
It has 17.5 pairs of repetitive pulses from low level (0/255). Since the peak value and time position of the framing pulse are defined, they can be used as fixed levels.

As an example, the level of $ i (255/255) -i in FIG.
i level (0/255)} can be used as a fixed level, but the input signal of the amplifier 13 varies depending on the signal source, and the signal source, that is, the signal input to the input terminal 1 or 5 is a little large. May vary. To correct this and make it a normal value, after converting the fixed level of this difference into an analog signal with the D / A circuit 20,
By negatively feeding back the signal to the amplifier 13, the desired video signal level is controlled to be input to the A / D circuit 7.

The output signal of the A / D circuit 7 is further fed to the ringing detection circuit 14
Is input to The method of detecting this ringing is shown in FIG. FIG. 7a shows the leading part of the framing pulse (for easy illustration ... Since the framing pulse is defined, any part may be used). FIG. 7B shows the sampling clock when the optimum image is obtained, and FIGS. 7C and 7D show the waveforms when the phase of the sampling clock is advanced and delayed, respectively. When the phase of the sampling clock is optimal, ringing does not occur because sampling is performed at the point of point in FIG. 7a. However, as shown in FIG. 7c, when the phase of the sampling clock advances, sampling is performed at the point x,
It is higher than the predetermined level by A. On the contrary, when the phase of the sampling clock is delayed, B is lowered because the sampling is performed at the 0 point. As described above, since the output of the A / D circuit 7 is set to a normal value by the negative feedback circuit, for example, the absolute value level at point i in FIG. By comparing, the magnitude of the ringing amount can be accurately detected as a difference from the predetermined value.

The ringing detection circuit 15 detects this ringing amount,
The detected output is added to the adder 9 as phase addition data. The adder circuit 9 adds the ringing detection output of the A / D circuit 7 and the detection output of the phase difference detection circuit 8. The added output is integrated by the integrating circuit 10 and then added to the VCO 11 to control the phase of the sampling clock of the A / D circuit 7. That is, the sampling clock is phase-controlled (ideally, the sampling clock should be brought to the state of FIG. 7b) so that the ringing level of FIG. 7a approaches the minimum.

EFFECTS OF THE INVENTION As described above, according to the present invention, the input level of the A / D circuit is automatically made constant for any input signal, and the phase of the sampling clock of the A / D circuit is changed to that of the video signal. Since the phase can be controlled to minimize the ringing, the best image can be obtained with the optimum video amplitude.

[Brief description of drawings]

FIG. 1 is a block diagram of an automatic ringing removal circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a transmission / reception system, FIG. 3 is a block diagram of a conventional ringing removal circuit, and FIG. 4 is horizontal synchronization. Waveform diagram of signal and clock signal, Fig. 5 is video signal, sampling clock waveform and output waveform diagram of A / D circuit, Fig. 6 is waveform diagram of framing pulse signal, Fig. 7 is framing pulse waveform and sampling clock pulse It is a waveform diagram of. 1 ... input terminal from the transmitting side, 2 ... FM demodulator, 3 ...
De-emphasis circuit, 4 ... Input switching circuit, 5 ... Baseband input terminal, 6 ... LPF, 7 ... A / D circuit, 8 ...
... Phase difference detection circuit, 9 ... Adder, 10 ... Integrator, 11 ...
… VCO, 12 …… A / D output, 13 …… Amplifier, 14 …… Fixed level detection, 15 …… Ringing detection, 16 …… Phase addition data adjustment circuit, 20 …… D / A circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshihiro Miyoshi 1006 Kadoma, Kadoma-shi, Matsushita Electric Industrial Co., Ltd. (72) Inventor Eiichi Hira, 1006 Kadoma, Kadoma-shi, Matsushita Electric Industrial Co., Ltd. (72) Invention Yuichi Ninomiya, 1-10-11 Kinuta, Setagaya-ku, Tokyo, Japan Broadcasting Technology Laboratory (72) Inventor Yoshimichi Otsuka 1-10-11 Kineta, Setagaya-ku, Tokyo, Japan Broadcasting Corporation Broadcasting Technology Laboratory (72) Inventor Ikinori Yoshinori, 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Broadcasting Research Laboratories, Japan Broadcasting Corporation (56) Reference JP-A-61-94415 (JP, A)

Claims (1)

(57) [Claims] 1. An FM demodulation means for demodulating a sub-sampled input FM video signal into a base band signal, a demodulation of a base band input video signal which is not pre-emphasized and the sub-sampled input FM video signal. An input switching circuit for switching the generated signal, an amplifier to which the video signal selectively switched by the input switching circuit is input, an analog-digital conversion circuit for converting an output signal of the amplifier into a digital signal, A phase error detection circuit for detecting a phase error of the sub-sampling clock of the analog-digital conversion circuit by a horizontal synchronizing signal added to the input signal, and a fixed level for detecting a fixed level from the output signal of the analog-digital conversion circuit. An analog output signal from the detection circuit and the fixed level detection circuit. Digital-analog conversion circuit for converting the output signal of the digital-analog conversion circuit to the amplifier, and a ringing level by comparing the output signal of the analog-digital conversion circuit with a predetermined level value. A ringing level detection circuit for detecting an amount, an adder for adding the detection output of the phase error and the detection output of the level amount of the ringing, an integrator for integrating the output signal of the adder, and A voltage-controlled oscillator for controlling an oscillation phase by an output signal to generate the sampling clock for the analog-to-digital conversion circuit; a two-dimensional interpolation circuit for reproducing a signal missing by sub-sampling processing by interpolation; Convert the output of the 2D interpolation circuit into an analog signal for display on a display device A digital-analog conversion circuit, and by correcting the variation in the size of the input video signal by the negative feedback signal from the feedback circuit and by using the detection output of the ringing amount as the phase addition data, the phase of the sampling clock can be ringed. An automatic ringing removal circuit, which is controlled to be minimum and automatically removes ringing signal components.