JPS5893287A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable to control the threshold voltage of a semiconductor device to the desired value against an MOS transistor of ultrafine size by controlling the thickness of an insulating film of the gate widthwise end of the surface of an element forming region. CONSTITUTION:The element forming region of a semiconductor substrate 11 is covered with a mask 12, and the substrate 11 is etched to form a recess having substantially vertical side wall at the substrate 11. An impurity of the same conductive type as the substrate 11 is implanted, thereby forming an inversion preventive layer 13. An SiO2 film 14 is buried in the field region in the state that the groove 15 is formed at the periphery. An SiO2 film 16 is accumulated to bury the groove 15, and a resist 17 is covered thereon to flatten the surface. Thereafter, the resist 17 and the film 16 are etched under the same conditions to become the equal etching speed, and the element forming region is exposed. Then, the element forming region is etched in this state, thereby forming a recess which is formed of an oblique surface 18 and a flat surface 19. When the surface is then oxidized, a gate oxidized film 20 of thick shape of section can be obtained at the end of the element forming region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an MO8 type semiconductor device in which a relatively thick field insulating film is buried in a field region so as to have a flat surface, and a method for manufacturing the same.

[Technical background of the invention]

Semiconductor devices using silicon as a semiconductor, especially MOS
In a type semiconductor device, a thick insulating film is formed in a so-called field region between elements in order to eliminate insulation defects due to parasitic channels and to reduce parasitic capacitance.

A selective oxidation method is conventionally well known as such an element isolation method. This is an oxidation-resistant mask for the element formation area.
Typically, this technique involves forming a thick oxide film selectively only in the field region by using a silicon nitride film and performing high-temperature oxidation.However, in this selective oxidation method, during the high-temperature oxidation, The field oxide film is embedded in the shape of a bird's beak from the lower end of the silicon nitride film.This causes dimensional errors in the element formation area and further impedes high integration of multiplication circuits.Also, the field area and the boundary between the element formation region has a thickness of about 03 to 0.5, a
A surface step of 8 degrees is formed. This surface step caused a decrease in phosphorography accuracy after selective oxidation and a decrease in the reliability of the metal arrangement at the surface step.

On the other hand, a method for forming a thick oxide film for isolation between elements without the above-mentioned bird's beaks or surface steps is the BOX method (iuring oxide 1nto oxide film).
3i11con Grove). The steps of this BOX method will be briefly explained below using FIG. As shown in FIG. 1(a), for example, a silicon substrate 8!1ζ is formed by using a normal photolithography process, covering the element formation region with a mask 2, and then covering the silicon substrate 1 in the field region.
Etch to a depth corresponding to the desired field dielectric thickness by 4".

Next, as shown in (b), using the mask 2, an impurity of the same electric type as the silicon substrate 1 is added to prevent field inversion.
For example, in the case of a P-type substrate, boron ions are implanted to form the anti-inversion layer 3. After that, as shown in (c), the lift
A silicon oxide film 4 is formed in the field area by off-processing.
It is buried with a groove 5 formed around the periphery. This lift
The 11'1 step is carried out, for example, as follows.

First, a plasma CVD 5in2 film is deposited on the entire surface, and then etched with an ammonium fluoride solution for about 1 minute. At this time, the plasma CVD 5in2 film deposited on the side walls around the element formation region is etched more rapidly than the 8102 film in other parts, so the Si on the 1111 film wall
The Ox film is selectively removed and grooves 5 are formed. Thereafter, when the mask 2 on the element formation region is removed, the plasma CVD Sin film deposited on the mask is removed, resulting in the structure shown in FIG. 1(C). Next, as shown in (d), CVD5iotllR is applied to the entire surface so as to fill the groove 5.
6 is deposited, and a film 8 such as a resist that is fluid and has the same etching rate as the 810□ film 6 in the etching process described later is deposited so as to fill the recesses 7 on the surface and flatten the surface. Apply and form. Thereafter, as shown in (e), the organic material pss and the CVD 5jOt film 6 are uniformly etched to expose the element formation region.

In the BOX method, by using reactive ion etching to etch the silicon $ plate, the dimensions of the device region are defined by the dimensions of the mask formed in the photolithography process, and the difference in dimension conversion of the device region is reduced to zero. can do.

Furthermore, since the surface can be made flat, the accuracy of phosphorography and the reliability of wiring are significantly improved.

[Problems with background technology]

However, using this OX structure, minute dimensions,
For example, when manufacturing a MOS (MOS) transistor with a gate width of 1 μm or less, the potential is higher at the edge of the surface of the element formation region and is more likely to be reversed than at the center surface of the element formation region.
Therefore, the threshold voltage of the transistor decreases. In this way, the threshold voltage of a MOS transistor depends on the gate width, which hinders integration.

[Purpose of the invention]

The present invention was made in view of the drawbacks of the BOX method mentioned above.
It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that eliminate the above-mentioned drawbacks by controlling the thickness of the insulating film at the ends in the gate width direction on the surface of the element forming region.

[Summary of the invention]

In the present invention, after a field insulating film is buried by the BOX method, the surface of the element formation region is subjected to, for example, anisotropic etching. As a result, four portions having a constant angle of 1 determined by the crystal orientation are formed at the end of the element forming region. When a gate oxide film is formed in this state, the oxidation rate of the sloped surface is higher than that of the flat surface of the intermediate part of the element forming region, so that the gate oxide film is thicker than 18 < in the central part and thick in the &it part.
Formed with good reproducibility. As a result, even in a small-sized MOS transistor, the potential at the end portion in the gate width direction of the device region becomes approximately the same as that at the center portion, and the above-mentioned drop in threshold voltage is eliminated.

[Embodiments of the invention]

Examples of the present invention will be described below with reference to FIG.

As shown in FIG. 2(a), the semiconductor substrate has a plane orientation of λ
Using a normal photolithography process on the silicon substrate 11 of 100), the element forming region is covered with a mask 12, and the field region's fill is etched by an amount corresponding to the desired field insulating film thickness. At this time, if reactive ion etching is used as the etching method, the inversion prevention layer 13 is formed by implanting ions of an impurity perpendicular to the y direction, such as boron in the case of a P-type substrate. Thereafter, as shown in (b), a plasma CVD film 14 is formed as a first insulating film in the field region by lift-off processing, and grooves 14 are formed around the periphery.
5 is formed and embed it. Next, as shown in (C), a CV film is formed as a second insulating film so as to fill the groove 15.
A D8102 film 16 is deposited, and a fluid material such as a resist 17 is further applied so that the surface is flat.

Here, instead of the resist 17, a meltable glass film such as a phosphorus silicide glass +1-poron silicide glass film may be formed and then melted to form a flat film. Next, as shown in (d), the resist 17 and the CVD 5
The io2 film 16 is uniformly etched under etching conditions with equal etching speed to form an element formation region. In this state, the element formation region is etched using a mixed solution of potassium hydroxide and isopropyl alcohol. The mixed liquid is a plasma CVD SiO2 film 14 and a CvD
The 5102 film slag etches only the first silicon substrate at a speed that corresponds to the plane orientation of the crystal without etching T. is etched for about 1 minute, resulting in about 500 A-T etching, and as shown in (e), the diagonal plane orientation (111) -[71
11B and a concave portion consisting of a flat surface 19 (100) is formed. It is then oxidized in an oxygen atmosphere of about 900C. (111) from the (100) plane in the oxygen capsule atmosphere
The surface oxidation rate is high, and the CVD 5in2 film 16
Since the gate oxide film 20 is also oxidized from the expansion, a thick cross-sectional gate oxide film 20 is obtained at the end of the element formation region, as shown in (f). Thereafter, a MOS transistor is formed by a normal silicon gate process.

According to this embodiment, the portion where the gate oxide film is formed is
Before that, other materials such as λ, CVDSi□, film 16, etc. are not exposed, and the surface of the channel region is not contaminated by impurities because it is exposed by etching immediately before forming the oxide film.

Also, the step difference between the element formation region and the field region is approximately 1
Even if the voltage is less than 000 A, the potential at the end of the element formation region and the potential at the center can be made almost equal. This degree of unevenness on the substrate surface does not cause a decrease in dimensional accuracy in the subsequent lithography process or a decrease in reliability such as breakage of the metal wiring at the surface step portion.

In this example, a mixture of 11 um hydroxide and isopropyl alcohol was used for anisotropic etching of the element formation region, but the same effect can be obtained using other etching methods, such as a mixture of ethylenediamine and pyrocatechol. The effect of is Kl. Furthermore, even if this etching step is not p-oriented etching, similar sprouts can be obtained by etching so that the surface of the cord formation region becomes a concave portion.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to control the threshold voltage of a micro-sized MOS transistor to a desired value without impairing the characteristics of the conventional BOX method.

[Brief explanation of the drawing]

Figure 1 (al to (el) is a cross-sectional view showing the manufacturing process of a real film for element isolation using the conventional BOX method, and Figure 2 (a) to (el).
f) is a sectional view showing the manufacturing process of an embodiment of the invention. 11...Shi11 Con Motokatsu, 12...Mask, 13.
...Inversion prevention layer, 14...5io2 model (first insulating film), 15...! luck, 16...5102 film (second insulating film), 17... resist (flattening edge fa), 1g.
...Slope, 19...Flat surface, 20... Gate oxide film. Applicant's agent Patent attorney Takehiko Suzue 1) Figure 1 422-l-~ Me\
Φ Moan-

Claims (3)

[Claims] (1) In a semiconductor device in which a field insulating film is buried in a recess having a substantially vertical wall on the surface of a semiconductor substrate, and a MOS transistor is formed in a region surrounded by the field insulating film, the MOS transistor A semiconductor device characterized in that the gate insulating film is formed to be thicker at both ends in the gate width direction than at the center. (2) A step of forming a recess with vertical sidewalls in the field region of the semiconductor substrate, a step of burying a field insulating film in the recess so that the surface is flat, and a step of forming the substrate surface in the element formation region into a recess. and a step of forming a MO8I-transistor by forming a gate oxide film in this element formation region so that the film thickness on the slopes at both ends in the gate width direction is thicker than that at the center. A method for manufacturing a semiconductor device, comprising: (3) The process of embedding the field insulating film in the recess is as follows:
A step of forming a first insulating film in the recess with a groove formed around the recess by a lift-off method, a step of forming a second insulating film over the entire surface so as to fill the groove, and a step of forming a second insulating film over the entire surface so as to fill the groove. a step of uniformly etching this film and the second insulating film under etching conditions with equal etching rates until the substrate surface of the element forming region is exposed; A method of manufacturing a semiconductor device according to claim 2, comprising: