JPS5892243A - Package for fet - Google Patents

Package for fet

Info

Publication number
JPS5892243A
JPS5892243A JP56191173A JP19117381A JPS5892243A JP S5892243 A JPS5892243 A JP S5892243A JP 56191173 A JP56191173 A JP 56191173A JP 19117381 A JP19117381 A JP 19117381A JP S5892243 A JPS5892243 A JP S5892243A
Authority
JP
Japan
Prior art keywords
conductive layer
fet
electrode
gate electrode
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56191173A
Other languages
Japanese (ja)
Other versions
JPS6255722B2 (en
Inventor
Michio Irie
三千夫 入江
Shigeo Iki
伊木　茂男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56191173A priority Critical patent/JPS5892243A/en
Publication of JPS5892243A publication Critical patent/JPS5892243A/en
Publication of JPS6255722B2 publication Critical patent/JPS6255722B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13063—Metal-Semiconductor Field-Effect Transistor [MESFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Microwave Amplifiers (AREA)

Abstract

PURPOSE:To improve the band characteristic by the reduction of the input reflection coefficient of a GaAs MESFET, by providing an inductance to a source. CONSTITUTION:The GaAs MESFET chip 6 is mechanically connected to a conductive layer 2 for source electrode, and the source electrode 7, the second gate electrode 8, the first gate electrode 9 and drain electrode 10 are connected respectively to the conductive layer 2 for source electrode, conductive layer 3 for the second gate electrode, conductive layer 4 for the first gate electrode and conductive layer 5 for drain electrode by metallic fine wires 11. Further, a conductive layer 12 for inductance wherein the conductive layer for source electrode is extended is provided.

Description

【発明の詳細な説明】 この発明は電界効果トランジスタ（以下ＦＥＴと略す）
用パッケージに係り、詳しくは入力反射係数低減用のノ
ースイングクタンスを内蔵したＦＥＴ用パッケージに関
するものである。[Detailed Description of the Invention] This invention relates to a field effect transistor (hereinafter abbreviated as FET)
The present invention relates to a FET package, and more specifically, to an FET package that includes a built-in no-swing factor for reducing the input reflection coefficient.

第１図は、従来形のデュアルゲー）　ＦＥＴ用パッケー
ジの内部構造の一例を示す平面図でめる０第１図に示す
ように、セラ建ツクなどからなる絶縁性基板ｉｌ＋の一
生面上に、その中央部から一側部にかけてソース電極用
導電層（２）が例えばメタライズにより形成される０絶
縁性基板（１）の−主面上のソース電極用導電層（２）
の向い側及び左右両側には、電気的に絶縁されて、第２
ゲート電極用導電層（３）、第１ゲート電極用導電層（
４）、ドレイン電極用導電層（６）がそれぞれ形成され
る０ 第２図は第１図に示すＦＥＴ用パッケージに、ガリウム
ヒ素ショットキ障壁形電界効果トランジスタ（以下Ｇａ
Ａａ　ＭＥＳ　ＦＥＴと略す）チップを装着した場合の
一実施例を示す平面図である。第２図においてソース電
極用導電層（２）にｕ　ＧａＡｓ　ＭＥＳ　ＦＥＴチッ
プ（６）が機械的に接続され、ＧａＡａ　ＭＥＳ　ＦＥ
Ｔチップ（６）上のソース電極（７）、第２ゲート電極
（８）、第１ゲート電極（９）及びドレイン電極頭は、
それぞれソース電極用導電層（２）、第２ゲート電極用
導電層（３）、第１ゲート電極用導電層（４）及びドレ
イン電極用導電層（５）に、金属細線αυで接続される
。Figure 1 is a plan view showing an example of the internal structure of a conventional dual-gate FET package. , the source electrode conductive layer (2) is formed on the -main surface of the insulating substrate (1), for example, by metallization, from the center to one side of the source electrode conductive layer (2).
On the opposite side and on both left and right sides are electrically insulated second
Conductive layer for gate electrode (3), conductive layer for first gate electrode (
4) and a conductive layer (6) for the drain electrode are respectively formed.
FIG. 2 is a plan view showing an example in which an Aa MES FET (abbreviated as Aa MES FET) chip is attached. In FIG. 2, a uGaAs MES FET chip (6) is mechanically connected to the source electrode conductive layer (2), and the GaAa MES FE
The source electrode (7), second gate electrode (8), first gate electrode (9) and drain electrode head on the T chip (6) are as follows:
The conductive layer for the source electrode (2), the conductive layer for the second gate electrode (3), the conductive layer for the first gate electrode (4), and the conductive layer for the drain electrode (5) are respectively connected to the thin metal wire αυ.

このような、従来形のＧａＡ＠　Ｍｉｓｓ　ＦＥＴは、
数ＧＨ３□のマイクロ波帯において低雑音、高利得の優
れた特性を有する素子として広く実用化されているが、
近年、その低雑音、高利得特性に着目して、ＩＧＨｚ帯
以下のＵＨＦ帯にも適用する試みがなされている。This kind of conventional GaA@Miss FET is
It has been widely put into practical use as an element with excellent characteristics of low noise and high gain in the microwave band of several GH3□.
In recent years, attention has been focused on its low noise and high gain characteristics, and attempts have been made to apply it to the UHF band below the IGHz band.

しかし、このような従来形のＧａＡｓ　ＭＥＳ　ＦＥＴ
をＵＨＦ帯で用いようとする場合には次のような問題点
がめった。すなわち、ＧａＡｓ　ＭＫＳ　ＦＥＴは、Ｕ
ＨＦ帯において本質的に入力反射係数が大きく、応用機
器のインピーダンス（通常５００）と整合をとることが
非常に困難となり、特に、広帯域特性ｔ−要求される場
合には致命的な欠点となる。However, such conventional GaAs MES FET
When attempting to use this in the UHF band, the following problems were encountered. That is, the GaAs MKS FET is
In the HF band, the input reflection coefficient is essentially large, making it very difficult to match the impedance (usually 500) of the applied equipment, which is a fatal drawback especially when broadband characteristics are required.

本発明は、上記欠点に鑑みてなされたものであり、ソー
スにインダクタンスを設けることにより、ＧａＡｓ　Ｍ
ＫＳ　ＦＥＴの入力反射係数を低減させて、帯域特性を
改善することのできるＦＥＴ用パッケージを提供しよう
とするものである。The present invention has been made in view of the above-mentioned drawbacks, and by providing an inductance in the source, GaAs M
The present invention aims to provide a FET package that can improve the band characteristics by reducing the input reflection coefficient of the KS FET.

以下、図面に基づいてこの発明を説明する。The present invention will be explained below based on the drawings.

第３図は、本発明のＦＩＴ用パツケー゛ジの一実施例を
示す平面図である。第３図において、第１図と対応する
部分には同−符号全村して示したが、この実施例のＦＥ
Ｔ用パッケージにおいては、ソース電極用導電層を延長
したインダクタンス用導電層＠を設けている。FIG. 3 is a plan view showing an embodiment of the FIT package of the present invention. In FIG. 3, all parts corresponding to those in FIG. 1 are shown with the same reference numerals.
In the T package, an inductance conductive layer @ which is an extension of the source electrode conductive layer is provided.

第４図は、第３図のＦＥＴ用パッケージにＧａＡａＭＥ
Ｓ　ＦＥＴチップを装着した場合の一実施例を示す平面
図である。第４図において、第２図と対応する部分には
同一符号を付して示したが、この実施例のＧａＡｓ　Ｍ
ＥＳ　ＦＥＴにおいては、ソースのインダクタンスが、
第２図のそれに比べてかなり大きくなっている。Figure 4 shows GaAaME in the FET package of Figure 3.
FIG. 3 is a plan view showing an example in which an S FET chip is attached. In FIG. 4, parts corresponding to those in FIG. 2 are denoted by the same reference numerals.
In ES FET, the source inductance is
It is considerably larger than that in Figure 2.

従って、このソースのインダクタンスの効果により、Ｕ
ＨＦ帯においても入力反射係数を低減することができ、
応用機器とのインピーダンス整合が容易になり、帯域特
性が改善される。Therefore, due to the effect of this source inductance, U
The input reflection coefficient can be reduced even in the HF band,
Impedance matching with applied equipment becomes easier and band characteristics are improved.

なお、このソースのインダクタンスにより、雑音特性、
利得特性は多少悪化するが、ＵＨＦ帯においてはこれら
の特性は充分余裕があるので、入力反射係数の低減を考
慮すれば総合的には非常に実用性の高い特性を得ること
ができる。Note that due to the inductance of this source, the noise characteristics
Although the gain characteristics deteriorate to some extent, these characteristics have sufficient margin in the UHF band, so if the reduction of the input reflection coefficient is taken into consideration, very practical characteristics can be obtained overall.

以上−１詳細に説明し九ように、本発明のＦＥＴ用パッ
ケージにＧａＡｓ　ＭＥＳ　ＦＥＴチップを装着すれば
、ソースにインダクタンスを内蔵しているため、ＵＨＦ
帝においても入力反射係数の小さい、帯域特性の優り、
ｆｔ　ＧａＡｓ　ＭＥＳ　ＦＥＴを得ることができる。As explained above in detail in 1-1, if a GaAs MES FET chip is attached to the FET package of the present invention, the UHF
Excellent band characteristics with small input reflection coefficient,
ft GaAs MES FETs can be obtained.

なお、本発明は、デュアルゲートＦＥＴのみならず、シ
ングルグー）　ＦＥＴにも適用できるのはもちろんであ
る。Note that the present invention is of course applicable not only to dual gate FETs but also to single gate FETs.

【図面の簡単な説明】[Brief explanation of the drawing]

［１図は、従来形のデュアルグー）ＦＥＴ用パッケージ
の内部構造の一例を示す平面図、第２図はｊｌＩ１図に
示すＦＥＴ用パッケージにＧａＡｓ　ＭＥＳ　ＦＥＴチ
ップを装着した場合の一実施例を示す平面図、第３図は
本発明のＦＥＴ、用パッケージの内部構造の一例を示す
平面図、第４図は第３図のＦＩＴ用パッケージＫ　Ｇａ
Ａｓ　ＭＥＳ　ＦＥＴチップを装着した場合の一実施例
を示す平面図である。 図中＋１）は絶縁性基板、（２）はソース電極用導電層
、（３）は第２ゲート電極用導電層、（４）は第１ゲー
ト電極用導電層、（５）はドレイン電極用導電層、（６
）はＧａＡｓ　ＭＥＳ　ＦＩＳＴチップ、（７）はソー
ス電極、＋８１／ｆｉ第２ゲート電極、（９）は第１ゲ
ート電極、（１０）はドレイン電極、（ロ）は金属細線
、Ｑｊｌはインダクタンス用導電層である。 なお、図中の同一符号は同一または相当部分を示す０ 代理人　葛野信− 第１図 第２図 第３図 第４図[Figure 1 is a plan view showing an example of the internal structure of a conventional dual-type FET package, and Figure 2 shows an example in which a GaAs MES FET chip is attached to the FET package shown in Figure 1. 3 is a plan view showing an example of the internal structure of the FET package of the present invention, and FIG. 4 is the FIT package KGa of FIG. 3.
FIG. 2 is a plan view showing an example in which an As MES FET chip is attached. In the figure, +1) is an insulating substrate, (2) is a conductive layer for the source electrode, (3) is a conductive layer for the second gate electrode, (4) is a conductive layer for the first gate electrode, and (5) is for the drain electrode. conductive layer, (6
) is a GaAs MES FIST chip, (7) is a source electrode, +81/fi second gate electrode, (9) is a first gate electrode, (10) is a drain electrode, (b) is a thin metal wire, and Qjl is a conductor for inductance. It is a layer. In addition, the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 絶縁性基板と、この絶縁性基板の一生面上にそれぞれ形
成され互いに電気的に絶縁された第１ゲート電極用導電
層、第２ゲート電極用導電層、ドレイン電極用導電層、
ソース電極用導電層及び上記ソース電極用導電層から延
長されたインダクタンス用導電層とを備えてなる電界効
果トランジスタ用パッケージ。an insulating substrate; a first gate electrode conductive layer, a second gate electrode conductive layer, and a drain electrode conductive layer formed on the entire surface of the insulating substrate and electrically insulated from each other;
A package for a field effect transistor comprising a conductive layer for a source electrode and a conductive layer for inductance extending from the conductive layer for the source electrode.
JP56191173A 1981-11-27 1981-11-27 Package for fet Granted JPS5892243A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56191173A JPS5892243A (en) 1981-11-27 1981-11-27 Package for fet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56191173A JPS5892243A (en) 1981-11-27 1981-11-27 Package for fet

Publications (2)

Publication Number Publication Date
JPS5892243A true JPS5892243A (en) 1983-06-01
JPS6255722B2 JPS6255722B2 (en) 1987-11-20

Family

ID=16270108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56191173A Granted JPS5892243A (en) 1981-11-27 1981-11-27 Package for fet

Country Status (1)

Country Link
JP (1) JPS5892243A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60236508A (en) * 1984-05-10 1985-11-25 Dx Antenna Co Ltd Wide band amplifier
JPH02143604A (en) * 1988-11-25 1990-06-01 Nec Corp Ultrahigh frequency amplifier
US5164877A (en) * 1990-02-23 1992-11-17 Fuji Electric Co., Ltd. Semiconductor device
JP2008056389A (en) * 2006-08-30 2008-03-13 Komori Corp Belt-like body passing through method and its device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60236508A (en) * 1984-05-10 1985-11-25 Dx Antenna Co Ltd Wide band amplifier
JPH02143604A (en) * 1988-11-25 1990-06-01 Nec Corp Ultrahigh frequency amplifier
US5164877A (en) * 1990-02-23 1992-11-17 Fuji Electric Co., Ltd. Semiconductor device
JP2008056389A (en) * 2006-08-30 2008-03-13 Komori Corp Belt-like body passing through method and its device

Also Published As

Publication number Publication date
JPS6255722B2 (en) 1987-11-20

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