JPS5891599A - Storage controlling system - Google Patents

Storage controlling system

Info

Publication number
JPS5891599A
JPS5891599A JP56190253A JP19025381A JPS5891599A JP S5891599 A JPS5891599 A JP S5891599A JP 56190253 A JP56190253 A JP 56190253A JP 19025381 A JP19025381 A JP 19025381A JP S5891599 A JPS5891599 A JP S5891599A
Authority
JP
Japan
Prior art keywords
storage device
battery
power supply
circuit
voltage drop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56190253A
Other languages
Japanese (ja)
Inventor
Hironori Yamamoto
浩憲 山本
Shigeo Tosaka
登坂 茂男
Hideki Sugiyama
秀樹 杉山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56190253A priority Critical patent/JPS5891599A/en
Publication of JPS5891599A publication Critical patent/JPS5891599A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/28Supervision thereof, e.g. detecting power-supply failure by out of limits supervision

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Stand-By Power Supply Arrangements (AREA)

Abstract

PURPOSE:To easily cope with a temporary voltage drop, by providing a means for checking an error of a data read out from a storage device, when switching the storage device to a back-up battery at the time of disconnection of an electric power supply, and detecting a voltage drop of the battery. CONSTITUTION:When a back-up battery 2 is turned on at the time of disconection of an electric power supply, a controlling circuit 5 operates, a storage device supplies an address signal, a storage address is driven in order, and a stored data is read out in order. In case when stored contents have been broken down due to an operating voltage drop, a parity checking circuit 11 automatically checks whether it is a pairty error or not, at the time of read-out operation. When an error is detected by the parity checking circuit, an alarm is raised from the controlling circuit 5, the operation is discontinued, and the stored contents are corrected. In this way, a voltage drop is detected easily.

Description

【発明の詳細な説明】 本発明は記憶装置を電源切断時パックアッグ用電INK
切替え九場合、そoIE源の電圧低下を藺単に検出で龜
ゐ記憶制御方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides storage devices with
In the case of switching, the voltage drop of the IE source is simply detected and the storage control method is involved.

従来、記憶装置を有する偏置において、電源切断時も、
そO記憶内容を保持するため、バックアップ用電池を設
けて切替える方式が用いられている。第1図はこの場合
の電池切れ検出方式を示す。
Conventionally, in an eccentric system with a storage device, even when the power is turned off,
In order to retain the memory contents, a method is used in which a backup battery is provided and switched. FIG. 1 shows a dead battery detection method in this case.

すなわち、電源回路1と電池2を電源切替回路5で切替
え記憶回路4に供給する。電源切替回路3によルミ源投
入時は電#A回路1からの電力を記憶装置4に供給し、
電源切断時は電池2からの電力を記憶装置114に供給
し、記憶内容を保持する。この場合、電池2の電圧が記
憶装置4の動作電圧以下となった場合その記憶内容が破
壊されることがあるため、電池2の電圧が記憶装置4の
動作電圧以下となったことを検出する必要がある。この
ため、記憶装置4の動作電圧に対応する電圧を発生する
基準電圧回路6を設け、この基準電圧と電池2の電圧を
電圧比較回路7で比較し、その結果を劃−回路5に送っ
て駿視し、電池電圧が基準電圧まで低下したことを検知
した時アラーム等を発生する。このように基準電圧と比
較する方式は基準電圧が必要とな多回路が複雑となゐほ
か、電池に充電回路を接続した場合Ka電圧低下の検出
が固層となるという問題がある。
That is, the power supply circuit 1 and battery 2 are supplied to the switching storage circuit 4 by the power supply switching circuit 5. When the Lumi source is turned on, the power supply switching circuit 3 supplies power from the power supply #A circuit 1 to the storage device 4,
When the power is turned off, power from the battery 2 is supplied to the storage device 114 to retain the stored contents. In this case, if the voltage of the battery 2 becomes less than the operating voltage of the storage device 4, the stored contents may be destroyed, so it is detected that the voltage of the battery 2 becomes less than the operating voltage of the storage device 4. There is a need. For this purpose, a reference voltage circuit 6 is provided that generates a voltage corresponding to the operating voltage of the storage device 4, and a voltage comparison circuit 7 compares this reference voltage with the voltage of the battery 2, and sends the result to the voltage comparison circuit 5. It monitors the battery voltage and generates an alarm when it detects that the battery voltage has dropped to the reference voltage. This method of comparing with a reference voltage has the problem that the multiple circuits that require the reference voltage are complicated, and when a charging circuit is connected to the battery, the detection of a drop in the Ka voltage becomes static.

本発明の目的はバックアップ用電源の電圧低下を検出す
る丸めの簡単で確実な記憶制御方式を提供することであ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide a simple and reliable storage control method for detecting a voltage drop in a backup power supply.

前記目的を達成するため、本楯明の記憶制御方式は記憶
装置の格納内容に従って動作する制御回路を有し、記憶
装置の供給電源切断時にその記憶内容を保持するためバ
ックアップ用電源から記憶”装置に給電する方式におい
て、前記記憶装置から続出されるデータのlu)をチェ
ックする手段を具え、前記制御回路は供給電源が投入さ
れ走時繊記憶装置からデータを読出すことによル、切替
給電したバックアップ用電源の電圧低下を検出すること
七〇lkとするものである。
In order to achieve the above object, the storage control method of the present invention has a control circuit that operates according to the stored contents of the storage device, and in order to retain the storage contents when the power supply to the storage device is cut off, the storage control method of the present invention has a control circuit that operates according to the stored contents of the storage device. In the power supply method, the control circuit includes means for checking the lu of data successively outputted from the storage device, and the control circuit switches the power supply by reading data from the running time storage device when the power supply is turned on. It is designed to detect a voltage drop in the backup power supply at 70 lk.

以下装置@を実施例につき詳述する。The apparatus will be described in detail below with reference to examples.

H2図は本発明の実施例の構成説明図である。Figure H2 is a configuration explanatory diagram of an embodiment of the present invention.

同図に示すように、1本発明では電池電圧を基準電圧と
比較する方法をとらず、装置に電源が投入された時点で
、単に記憶装置の内容をチェツタし、チェックによnv
snがなければ装置の通常の運用動作となるようにした
ものである。すなわち、電源が投入もれると制御回路5
が動作し記憶装置4がアドレス領域を供給し、かつ順次
記憶アドレスを歩進して各アドレスに格納されたデータ
を撫次読出していくようにされる。パリティチェック回
路11は記憶装置4の1部の記憶素子が動作電圧低下の
ため内容破壊上ていれば、この読出し動作時にパリティ
誤)か否かを自動検査する。電池電圧の低下は徐々に起
ルかつ記憶素子の動作電圧低下特性もまちまちであるか
ら、一部の早期検出によp大部分を救済できることは非
常に有効である。
As shown in the figure, the present invention does not use a method of comparing the battery voltage with a reference voltage, but simply checks the contents of the storage device when the device is powered on, and checks the nv
If sn is not present, the device will operate normally. In other words, if the power is turned on or the control circuit 5
operates, the memory device 4 supplies an address area, and sequentially increments the memory addresses to sequentially read out the data stored in each address. The parity check circuit 11 automatically checks whether there is a parity error during the read operation if some of the storage elements of the storage device 4 are destroyed due to a drop in operating voltage. Since the battery voltage decreases gradually and the operating voltage decrease characteristics of the memory elements vary, it is very effective to be able to rescue most of the p by early detection.

このことはアク竜ス時の雑音による記憶内容の破壊検出
と同様に考えることができる。制御回路5が記憶装置4
に割付けられたアドレス領域からデータを続出しても、
アラーム信号がパリティチェック回路11かも供給され
ない場合は、電池2に障害がなかったものとして制御回
路5は通常の運用動作をする。パリティチェックは記憶
内容につき水平、―直、および両者の何れに対して行な
ってもよいし、記憶内容の全部または一部に対して行な
ってもよい。パリティチェック回路11で誤りが検出さ
れると、制御回路5かもアラームを発生し、結果として
動作を中断し記憶内容の修正が行なわれる。しかし記憶
内容によ6ては中断したくないような場合がある。
This can be thought of in the same way as the detection of destruction of memory contents due to noise during an attack. The control circuit 5 is the storage device 4
Even if data is continuously output from the address area allocated to
If the alarm signal is not supplied to the parity check circuit 11, the control circuit 5 assumes that there is no failure in the battery 2 and operates normally. The parity check may be performed on the stored contents horizontally, vertically, or both, and may be performed on all or part of the stored contents. When an error is detected in the parity check circuit 11, the control circuit 5 also generates an alarm, and as a result, the operation is interrupted and the stored contents are corrected. However, depending on the memory contents, there may be cases where it is not desirable to interrupt the process.

第s!IAはこのような場合に用いる本発明の他の実施
例の構成説明図で6石。すなわち、動作電圧の異なる記
憶装置41 e 4mを輯け、装置の電源が投入される
と、制御回路5が連続的に、記憶装置4凰。
No. s! IA is an explanatory diagram of another embodiment of the present invention used in such a case, and has 6 stones. That is, when the memory devices 41 e 4 m having different operating voltages are connected and the device is powered on, the control circuit 5 continuously operates the memory devices 41 e 4 m.

4mK同一アドレス信号を与え記憶データを続出す。4mK The same address signal is given to output stored data one after another.

−作電圧の高い方の記憶装置43のパリティを第2図と
同様にチェツタすることによp、動作電圧の低い方の記
憶装fll14sの記憶内lFO破雇による抜けを完全
に防止で龜ゐ。
- By checking the parity of the memory device 43 with a higher operating voltage in the same way as shown in FIG. 2, it is possible to completely prevent the omission of the memory IFO due to the failure of the memory device 14s with a lower operating voltage. .

菖4E線本発明の壜らに他の実施例の構成説明図である
。前述の実施例が記憶装置の記憶内容のデータ誤シをノ
(リテイによルテエツタしたのに対し、記憶内容の7オ
ーマブトたとえば最大値、最小値1桁歇等をチェックし
、パリティチェツタで検出できないデータ誤ルを検出す
る。すなわち、pI1図に示すようにフォー!ットテエ
ツタ回路12を設け、フォーマット異常のとき制御回路
5からアラームを発生することは第2図の場合と同様で
ある。このフォーマットチェック回路をパリティチェッ
ク回路と併用することもできる。
Iris 4E line It is a configuration explanatory diagram of another embodiment of the bottle of the present invention. In contrast to the above-mentioned embodiment, which checks data errors in the memory contents of the storage device by checking the data errors, the data errors in the memory contents of the storage device are checked using a parity checker. In other words, as shown in Figure PI1, a formatter circuit 12 is provided and an alarm is generated from the control circuit 5 in the event of a format error, as in the case of Figure 2. The check circuit can also be used in conjunction with a parity check circuit.

以上説明し丸ように、本発明によれば、記憶装置を電源
切断時バックアップ用電池に切替える場合、その電池の
電圧低下を記憶装置の記憶内容のデータ誤シをパリティ
またはフォーマットチェックで検出するものである。こ
れによシ、電池切れ検出回路が簡単とな多、一時的な電
圧低下(電源投入時には正常な電圧に復旧する場合)の
検出にも対処できる。
As described above, according to the present invention, when a storage device is switched to a backup battery when the power is turned off, a voltage drop in the battery is detected by parity or format checking to detect data errors in the storage contents of the storage device. It is. This simplifies the battery dead detection circuit and allows it to detect temporary voltage drops (when the voltage is restored to normal when the power is turned on).

【図面の簡単な説明】 第1図は従来例の構成説明図、lI&2IiAは本発明
の実施例の構成説明図、!I3図、第4図はそれぞれ本
発明の他の実施例の構成説明図でTo夛、図中、1は電
源回路、2は電池、5は電源切替回路、4゜41g4m
は記憶装置、5は制御回路、11はノ(リテイテエツク
回路、12紘フオ一!ツトチエツク回路を示す。
[Brief Description of the Drawings] Fig. 1 is an explanatory diagram of the configuration of a conventional example, lI & 2IiA is an explanatory diagram of the configuration of an embodiment of the present invention,! Figure I3 and Figure 4 are configuration explanatory diagrams of other embodiments of the present invention, respectively.In the figures, 1 is a power supply circuit, 2 is a battery, 5 is a power supply switching circuit, 4°41g4m
5 is a storage device, 5 is a control circuit, 11 is a retail check circuit, and 12 is a photo check circuit.

Claims (1)

【特許請求の範囲】[Claims] 記憶装置の格納内容に従って動作する制御回路を有し、
記憶装置の供給電源切断時にその記憶内容を保持するた
めバックアップ用電源から記憶装置に給電する方式Ks
Plnで、前記記憶装置から続出されるデータの電力を
チェックする手段を^え、前記制御回路が供給電源が投
入され走時賦記憶装置かもデータを続出して切替給電し
たバッタアップ用電#lの電圧低下を検出することを特
徴とすゐ記憶制御方式。
It has a control circuit that operates according to the contents stored in the storage device,
A method of supplying power to a storage device from a backup power source in order to retain the memory contents when the power supply to the storage device is cut off.
At Pln, a means for checking the power of data successively output from the storage device is provided, and the control circuit outputs data continuously from the running time storage device when the power supply is turned on and switches the power supply #l for the battery up. A memory control method that detects voltage drops.
JP56190253A 1981-11-27 1981-11-27 Storage controlling system Pending JPS5891599A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56190253A JPS5891599A (en) 1981-11-27 1981-11-27 Storage controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56190253A JPS5891599A (en) 1981-11-27 1981-11-27 Storage controlling system

Publications (1)

Publication Number Publication Date
JPS5891599A true JPS5891599A (en) 1983-05-31

Family

ID=16255054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56190253A Pending JPS5891599A (en) 1981-11-27 1981-11-27 Storage controlling system

Country Status (1)

Country Link
JP (1) JPS5891599A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61221668A (en) * 1984-01-12 1986-10-02 Hagiwara Denki Kk Detecting and processing system for backup voltage

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5360123A (en) * 1976-11-10 1978-05-30 Sanyo Electric Co Ltd Searching system for memory content
JPS56148796A (en) * 1980-04-18 1981-11-18 Hitachi Ltd Computer application device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5360123A (en) * 1976-11-10 1978-05-30 Sanyo Electric Co Ltd Searching system for memory content
JPS56148796A (en) * 1980-04-18 1981-11-18 Hitachi Ltd Computer application device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61221668A (en) * 1984-01-12 1986-10-02 Hagiwara Denki Kk Detecting and processing system for backup voltage

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