JPS5890757A - Complementary type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the P-N boundary region for realizing high integration density by providing the structure where the one electrode of treansistor to be formed on the substrate is included in the diffusion region of the opposite conductivity type to a semiconductor substrate. CONSTITUTION:A P well region 12 is provided on the N type semiconductor substrate 11 and the N channel MOS transistor TrN is formed on the region 12. Moreover, the N<+> type impurity diffusion region 16 is formed on the substrate 11, and an insulating layer 17 and gate electrode 18 are sequentially formed on the substrate 11 defined between this region 16 and region 12. The drain of TrP and the source 13a of TrN are connected, the gate electrode 18 of TrP and the drain 13b of TrN are connected, and a power source voltage Vss is supplied to the gate electrode 15 of TrN. According to such constitution, since the region 12 is used as the drain of TrP, operation of C-MOSTr can be realized with less area. Therefore, an element density for total area can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary semiconductor integrated circuit device that can miniaturize confectionery.

In recent years, complementary M08 (hereinafter abbreviated as C-MOS) circuits have been applied to various circuits because of their low power consumption. This circuit, for example, as shown in FIG.
, and transistors Tr, + Tr, with opposite polarity to each other are provided on the N-type substrate surface and the P-w@l1 surface, respectively.
t''P-N boundary region ΔX.

Figure 2 shows a load circuit with negative resistance constructed using the C-MO8 circuit described above.
A channel transistor TrN and a P-channel transistor Tr are connected in series, and the terminal of the transistor Tr is connected to the drain of the transistor TrP, and the terminal of the transistor Tr is connected to the drain of the transistor TrN.

Now, in the circuit as described above, the transistor Tr H
The potential of the two-tom on the drain side of 1vA, the transistor T
When the potential of node B on the drain side of r is set to V,
In the potential relationship of "AI=vA-vl≧0", this circuit exhibits negative resistance characteristics as shown in FIG. Figure 3: The value of K multiplied by vIn is the P-channel transistor Tr,
and N-channel type MO8) depending on each threshold voltage of transistor T r w, r O < V, , < v, s
It is possible to set it arbitrarily within the range of J. In this circuit, when the potential vAll exceeds vrn, the circuit is in an open state, and the current "AI" from node A to node B
does not flow. Further, when the potential vAl and vrnxD are also small, it operates as a negative resistance element, and a current IAI determined by the value of the potential vAm flows. The circuit described above can be converted to a dual power source v9. When applied to a complementary semiconductor device driven by vll□(vDD>v,ll), 1 is applied to node B@.
1 source potential V□ is supplied, and a power supply potential vDD is supplied to the pack dirt of the transistor Tr. A circuit in this case is shown in FIG.

FIG. 5 shows an example of the cross-sectional configuration of the circuit shown in FIG. 4. On the N-type semiconductor substrate 11 to which the potential vDD is applied,
A P-w@ll region 12 to which the potential II is applied is provided Next, on the P-W@ll region 12, an N+ impurity diffusion region 13 is provided which becomes the source and drain of the transistor.
m and 13b are formed, and an insulating layer 14 and a dart electrode 15 are sequentially disposed between the glume regions to form an N-channel type MOS transistor Tr. Further, on the N-type substrate 11, P+ impurity diffusion regions 16m and 16b, which will become the drain and source of the transistor, are formed, and an insulating layer 11.1'-) electrode 18 is sequentially disposed between these regions. Channel type M
O8) Transistor Tr.

form. Then, the power supply potential v is supplied to the drain 16a of the transistor Tr and the gate electrode 15 of the transistor Tr, and
The drain 13b of N and the gate electrode 18 of the transistor Tr are connected, and the source xs* of each transistor is connected.
pxt;bt - connect and configure.

However, although the conventional C-MO8 configuration described above has low power consumption, it requires a pair of P-channel and N-channel transistors, so the number of elements is lower than that of a single-channel circuit. Not only does this increase, but also it is necessary to separate and insulate the regions in which the P-channel transistor and the N-channel transistor are formed, so a P-N boundary region 4X is required, which increases the chip area. Further, there are drawbacks such as the manufacturing process becoming complicated.

In particular, as the integration of circuits progresses, each region of the P-channel and N-channel MO8) run source has become finer due to improvements in lithography technology, and the degree of integration has increased, but the P-N boundary region ΔX The factor that determines the distance is the withstand voltage between the P diffusion region 16b and the P-W@11 region 12,! Breakdown voltage between diffusion region 13& and N type substrate 11, P-W
・Since it is determined by the manufacturing precision of region 12, miniaturization is difficult. For this reason, the ratio of the area of the PN boundary region ΔX to the entire pattern becomes large, which poses a problem.

This invention was made in view of the above circumstances,
The purpose of this is to reduce the P-N boundary area by configuring one electrode of the transistor formed on the substrate to be included on the diffusion region of the opposite conductivity type to the semiconductor substrate, and to achieve high integration. An object of the present invention is to provide a complementary semiconductor integrated circuit device that can be

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 6 shows its configuration, in which a P-v@ll region 12 to which a power supply voltage V□ is applied is provided on an N-type semiconductor substrate 11 to which a power supply voltage vDD is applied, and the P-W @1
N+ impurity diffusion region I Ja e J on the 1 region 12
An insulating layer 14 and a dart electrode 15 are sequentially disposed between these regions to form an N-channel type MOS transistor Tr. In addition, a total of impurities are diffused on the N-type substrate 11. area 16
An insulating layer 17 and an r-meter electrode 18 are sequentially disposed on the substrate 11 between the diffusion region 16 and the P-well region 12 to form a P-channel type MO transistor Tr. And the top? The drain 16 of the transistor TrP and the transistor T
Connect the source ISa of r and connect the transistor Tr.
Dart electrode 1# of and P of transistor Tr

N drain I
Jjb is connected to the dirt electrode 1 of the transistor Tr.
5, the power supply potential v1. It is designed to supply

According to such a configuration, the P-well region 12 is
Since it is used as the drain of the channel type transistor Tr, the same operation as the structure shown in FIG. 5 can be realized with a small area. Therefore, the element density relative to the total area can be improved.

FIG. 7 shows another embodiment of the present invention, in which the drain 16b of the transistor Tr is connected to the substrate 11 and P-W@
It is provided on the boundary with area No. 11. According to such a configuration, it is possible to easily adjust the manufacturing density of the P-v.11 region, expand the depletion layer of the drain diffusion during operation, and adjust the characteristics of the transistor.

In each of the above embodiments, a circuit working as a negative resistance element has been described, but the circuit is not limited to this circuit, and of course can be implemented with various modifications.

As explained above, according to the present invention, since the semiconductor substrate, the trace conductivity type diffusion region, and one electrode of the transistor formed on the substrate are configured as an integrated region, the P-N boundary A complementary semiconductor integrated circuit device that can reduce the area and can be integrated into a tube is provided.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional diagram of a C-MOS transistor;
The figure shows a negative resistance circuit with a C-MO8 configuration.
The figure shows the current-voltage characteristic diagram for the circuit in Figure 2 above.
5 and 5 are a circuit diagram and a sectional configuration diagram thereof, respectively, when the circuit shown in FIG. 2 is actually constructed, and FIG. 6 is a sectional configuration diagram showing a complementary semiconductor integrated circuit device according to an embodiment of the present invention 7 are cross-sectional configuration diagrams showing other embodiments of the present invention. 11...Semiconductor substrate, IJ-w@ll region (impurity diffusion region), IJa, IJb...N+ diffusion region, 16m+16b*16...P
diffusion area. Applicant's representative Patent attorney Takehiko Suzue Figure 4 VSS Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] In a semiconductor integrated circuit device in which a complementary MOS (MOS) transistor is formed on a semiconductor substrate and a diffusion region of opposite conductivity type provided on this substrate, one electrode of the transistor diffused on the substrate is arranged opposite to the substrate. A complementary semiconductor integrated circuit device characterized in that it is formed as a region integrated with a conductive type diffusion region.