JPS63142845A - Detector for supply voltage - Google Patents

Abstract

PURPOSE:To limit the dispersion of detecting voltage to a small value by constituting a supply voltage detector of a reference-voltage generating circuit, in which a resistance element and a junction diode are connected in series between a first power terminal and a second power terminal, and a sense amplifier using an intermediate contact for the reference-voltage generating circuit as an input. CONSTITUTION:A reference-voltage generating circuit is constituted of a resistor R connected between a supply voltage terminal VDD as a first power terminal and a contact 1 and a P-N junction diode D, the contact 1 side of which is connected to an anode consisting of a P-type diffusion layer and the ground terminal side of which to a cathode composed of an N-well, between the contact 1 and a ground terminal as a second power terminal, and an inverter (a sense amplifier) using the input terminals of a PMOS transistor and NMOS transistor M1 and M2 as the contact 1 and output terminals thereof as a contact 2 is organized. When the supply voltage VDD of the inverter receiving an output from the contact 1 and being constructed of M1 and M2 lowers and logic threshold voltage reaches V1, an output from the inverter is inverted. VDD at that time is not affected by the circuit parameter of the reference-voltage generating circuit, and is affected only by the variation of the logic threshold of the inverter.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a power supply voltage detection circuit, and particularly to a power supply voltage detection circuit for a semiconductor integrated circuit.

[Conventional technology]

In order to reduce the power consumption of semiconductor integrated circuits, a method is sometimes taken in which the power supply voltage is lowered when the chip is in a dormant state. However, at this time, normal processing cannot be performed inside the chip, so a signal must be issued to indicate that the chip has entered a hibernation state.

Therefore, when the power supply voltage drops below a certain voltage V, it becomes “H”
A power supply voltage detection circuit is required that outputs "L" (or "H") when (or "L") rises above 1.

As shown in FIG. 8, a conventional power supply voltage detection circuit includes a reference voltage generation circuit consisting of a resistor R1 and an nMOS transistor M3 connected in series, and a pMOS transistor M4.
and an inverter consisting of an nMOS transistor M5.

The operation of the power supply voltage detection circuit according to the prior art will be explained below, but first the reference voltage generation circuit will be explained with reference to the IV characteristic diagram shown in FIG. The IV characteristic of transistor M3 is the curve shown by I=fts (V), and the IV characteristic of resistor R1 is
The characteristics are I = (Voo-V) when the power supply voltage is VDD
/R1, and the intersection of the two is the operating point. That is, the potential at this point represents the potential 6 of the contact point 6. When the power supply voltage is lower than the threshold voltage VTN of M3, that is, when Vl-ID≦VTN, M3 is cut off and no current flows through the reference voltage generation circuit, so V 6-V D
It is D.

When VDD>VTN, M3 begins to conduct, and 6 begins to become lower than VDD due to the voltage drop due to R1.

V oo＞＞V In TN, f+++5 near the operating point
Since the rate of change of (V) is large, V6 hardly increases even if VDD increases. This situation is shown in FIG.

Next, the behavior of the output cuff of the next stage inverter will be explained. V
When DD is sufficiently high, the potential of ■6 is sufficiently lower than the logic threshold of the inverter composed of M4 and M5, so contact 7
is output at "H", that is, the potential of VDD. vD
D goes down and V6-V on > V TP (
When V tp satisfies the condition of pMO3) (threshold voltage of transistor M4), M4 is cut off and the potential 7 of contact 7 is set to the potential of nMO3f to MOS transistor M5. The power supply voltage rises again, and V6-Voo<Va,
Then, M4 starts to conduct, and the current driving ability of M4 becomes M5.
When it exceeds that, the output cuff is reversed and "H" is output. The above situation is expressed by time on the horizontal axis in the 11th
It is a diagram.

[Problem that the invention seeks to solve]

The above-described conventional power supply voltage detection circuit uses a MOS transistor in the reference voltage generation circuit, and therefore has the disadvantage that the detection voltage is affected by the deviation of the threshold voltage during manufacturing.

[Means for solving problems]

The power supply voltage detection circuit of the present invention includes a reference voltage generation circuit in which a resistive element and a junction diode are connected in series between a first power supply terminal and a second power supply terminal, and a sense circuit whose input is an intermediate junction of the reference voltage generation circuit. Consists of an amplifier.

Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

R is the power supply voltage terminal VpD which is the first power supply terminal and contact 1
A resistor, D, is connected between contact 1 and the ground terminal, which is the second power supply terminal, with the contact 1 side connected to the anode made of the n-type diffusion layer, and the ground terminal side connected to the cathode made of the n-well. p-
R and D constitute a reference voltage generation circuit using an n-junction diode, Ml is a pMOS transistor, and M2 is an nMOSMOS.
The transistor and M2 have their input terminals connected to contacts 1. An inverter (sense amplifier) is configured with the output terminal as contact 2. FIG. 2 shows an IV characteristic diagram of R and D. The curve shown by I=fo(V) is the characteristic of D, I=(VDD-V)
, /R is the characteristic of R, and the intersection point indicates the operating point. At this time, the forward breakdown voltage of the p-n junction diode D is not affected by manufacturing conditions and is constant at 0.6 V when silicon is used as the material, and the current rises rapidly (dro (V)/clv is large), so the potential V1 of contact 1 is kept almost constant. The inverter composed of M1 and M2 receiving the output of contact 1 receives the power supply voltage VD.
When D decreases and the logic threshold voltage reaches ■1, the output is inverted. If VDD at this time is defined as Vth as shown in FIG. 3, then ■. does not depend on the circuit parameters of the reference voltage generation circuit, but only on the variation of the logic threshold of the inverter.

FIG. 4 shows an example of a pattern layout diagram of an LSI mask when this circuit is realized on a p-type semiconductor substrate made of silicon. 101 is an n-type diffusion layer pattern, 102 is an n-type diffusion layer pattern, 103 is an n-well region pattern, 104 is a polycrystalline silicon layer pattern, 105 is an aluminum wiring layer pattern, and 106 is a contact region pattern.

FIG. 5 is a cross-sectional view of a semiconductor chip in which the circuit of FIG. 1 is integrated on a semiconductor substrate, and shows a cross-sectional view of a wafer portion corresponding to the line AA' in FIG. 10 is a p-type semiconductor substrate made of silicon, 11 is an n-well region, 1
2 is an n-type diffusion layer, 13 is an n-type diffusion layer, 14 is a silicon oxide film, 15 is polysilicon, 16 is an interlayer insulating film, 17 is an aluminum wiring layer, and 18 is a passivation film.

The n-type diffusion layer 12-1 constitutes a resistor R, and the n-type diffusion layer 13
This is an example in which a p--junction diode D is formed by a p-n junction between the p-n junction and the n-well region 11, and I) a MOS transistor is formed in the n-well region not shown in this cross-sectional view. These n-well regions are formed in the same process, and
The type diffusion layer 12.degree. 12-1 is also formed in the same process, and the n-type diffusion layer 13 is formed in the same process as the source region and drain region of the pMO9) transistor.

FIG. 6 is a circuit diagram showing a second embodiment of the present invention.

R2 is a resistor connected between the power supply VDD and contact 3, DI and D2 are connected in series between contact 3 and the ground terminal, and the directions from contact 3 to contact 5 and from contact 5 to the ground terminal are the forward direction. p-n junction diode, M6 is 9MO3) transistor, Ml is nM.

The S transistors M6 and M1 constitute a sense amplifier consisting of an inverter whose input terminal is a contact 3 and whose output terminal is a contact 4.

FIG. 7 shows the behavior of the potential of each contact when the power supply voltage DD is changed. The potential V3 of contact 3 is 2 of Dl and D2.
Since it is clamped by two diodes, the potential is 1.2 V for two stages of diodes, and Vth can be set higher than when using one stage of diodes. That is, by adjusting the number of stages of diodes, the low voltage detection voltage can be adjusted. The rest is the same as the first embodiment, so detailed explanation will not be given again. In addition, 1. In the second embodiment as well, the resistor can be replaced with a depletion type transistor.

〔Effect of the invention〕

As described above, the present invention has the effect of suppressing variations in detected voltage by using the forward characteristics of a junction diode for potential clamping of a reference voltage generating circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
The IV characteristic diagram of the resistor R and diode D shown in the figure, and Figure 3 is the power supply voltage ■ of the circuit of Figure 1. A characteristic diagram showing the behavior of the voltage at each contact when D is changed, Figure 4 is a pattern layout diagram of an LSI mask when the circuit in Figure 1 is realized on a semiconductor substrate, and Figure 5 is a diagram of the pattern in Figure 1. FIG. 6 is a circuit diagram of the second embodiment of the present invention, and FIG. 7 is a cross-sectional view of a semiconductor chip when the circuit of FIG. 6 is integrated on a semiconductor substrate. FIG. Figure 8 is a circuit diagram of the conventional example, Figure 9 is an IV characteristic diagram of resistors R1 and M3 in Figure 8, and Figure 10 is a characteristic diagram showing the behavior of voltage at each contact when FIG. 11 is a characteristic diagram showing the behavior of the voltage at each contact when the power supply voltage VDD of the circuit of FIG. 8 is changed. 1-7... Contact, 10... P-type semiconductor substrate, 11.
...n-well region, 12.12-1...n-type diffusion layer,
13...n-type diffusion layer, 14...silicon oxide film, 1
5... Polycrystalline silicon film, 16... Interlayer insulating film, 1
7... Aluminum wiring layer, 18... Passivation film, 101... N-type diffusion layer pattern, 102...
・N-type diffusion layer pattern, 103... N well region pattern, 104... Polycrystalline silicon layer pattern, 105
... Aluminum wiring layer pattern, 106 ... Contact region pattern, D, Di, D2 ... Junction diode, Ml ... nMOS transistor, M2. M3・
...nMO8) transistor, M4...9MO3) transistor, M5...nMOS transistor, M6...
PMOS transistor, Ml...nMOS transistor, R, R1, R2...resistance. ＼－Ichiman Z Ward No. 7 Kou No. 10

Claims (1)

[Claims] Consisting of a reference voltage generation circuit in which a resistance element and a junction diode are connected in series between a first power supply terminal and a second power supply terminal, and a sense amplifier whose input is a contact point between the resistance element and the junction diode of the reference voltage generation circuit. A power supply voltage detection circuit featuring: