JPH03217915A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To heighten the inspection efficiency of an LSI by turning off a MOSFET on a DC path in a source voltage conversion circuit with an external signal when inspection is performed, to cut off a current, and enabling a standby current to be measured. CONSTITUTION:When a test mode signal TEST goes to H, the MOSFET M3 is turned on, and the MOSFET M4 is turned off, thereby, the gate voltage of the MOSFET M1 goes to Vcc, then, the M1 is turned off, and the DC path in a reference voltage generation circuit 1 is cut. Furthermore, a bias transistor M15 at a differential amplification stage is also controlled with the test mode signal, and an N-channel MOSFET M17 is connected between the gate terminal of the MOSFET M16 and the ground, and it is controlled to turn on and off with the test mode signal. A transmission gate TG is connected between an output node n2 at the differential amplification stage and the M16, which is controlled to turn on and off with the test mode signal.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit technology and a technology that is particularly effective when applied to a power supply voltage conversion circuit in a MOS integrated circuit. This invention relates to techniques that are effective when operating internal circuits.

[Prior Art] Currently, the process technology for semiconductor integrated circuits is transitioning from a 1 μm process to a submicron (0.5 μm) process, and it is expected that semiconductor devices will become increasingly finer in the future.

By the way, in LSIs with MOSFETs, as elements become smaller, the same power supply voltage (5
v), contrary to the scaling law, the MOSFET
Since a high voltage is applied to the gate electrode, many problems arise such as a short channel effect, an increase in hot carriers, and a decrease in the withstand voltage of the gate insulating film. Therefore, it has become difficult to use a power supply voltage of 5V in submicron process devices. However, in a system consisting of a plurality of LSIs, the use of a combination of LSIs with different power supply voltages increases costs, so it is desirable to be able to use a single power supply as much as possible. Therefore, in order to guarantee the reliability of the MOSFET, a memory was proposed in which a power supply voltage conversion circuit was installed inside the LSI, and the memory array part was driven at a low voltage such as 3.3V, which was internally stepped down from the external power supply voltage. (Refer to "Nikkei Microdevice J, March 1989 issue, pages 64 to 67, published by Nikkei BP)."

[Problems to be Solved by the Invention] In general, in MOSLSI, standby current flowing through logic circuits and memory circuits becomes almost zero when the circuit is not operating. Therefore, by measuring the standby current, it is possible to discover minute leakage currents caused by via holes or unetched metal layers, etc.
It is possible to identify products that are likely to become defective due to short circuits occurring in areas with bottle holes or etched residue during use, and to perform failure analysis on defective products.

However, in an LSI incorporating a conventional power supply voltage conversion circuit, the standby current cannot be measured because the power supply voltage conversion circuit has a DC current bus. Therefore,
It has been found that there is a problem in that product inspection and failure analysis cannot be performed efficiently by measuring standby current.

The main feature of the present invention is to enable easy product inspection and failure analysis by measuring standby current in an LSI that has a power supply voltage converter circuit inside which steps down an external power supply voltage.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a switch MOSFET that can be turned on and off by an external control signal is provided on a DC bus in a power supply voltage conversion circuit built into an LSI.

[Operation] According to the above-described means, during inspection, the MOSFET on the DC current bus in the power supply voltage conversion circuit is controlled by an external control signal.
By turning off the ET, the current in the power supply voltage conversion circuit is cut, making it possible to measure the standby current flowing through the internal logic circuits and memory circuits when the operation is stopped.
The above objectives of increasing inspection efficiency and facilitating failure analysis can be achieved.

[Embodiment] FIG. 1 shows an embodiment of a power supply voltage conversion circuit when a P-type silicon substrate is used as the semiconductor substrate.

In the figure, 1 is a reference voltage generation circuit, and 2 is an impedance conversion circuit using a differential amplifier circuit. When using a P-type silicon substrate, MO for miniaturized internal circuits
P-channel MOSFET of SFET
is formed on the N-well region, and this N-well region is supplied with a voltage of 3.3V, which is lower than the external power supply voltage of 5V, in order to guarantee withstand voltage.
An internal voltage ■int such as is applied.

Therefore, in this embodiment, the power supply voltage conversion circuit is constructed of P-channel MOSFETs Ml and M2 connected in series, and the power supply voltage VcC is divided by the ratio of their on-resistances to generate a reference voltage.
, M2 and P-channel MOSFETs constituting the impedance conversion circuit 2.
It is formed on an N-well separated from the wells to ensure separation between the wells.

In order to enable the DC current bus in the power supply voltage conversion circuit 1 to be disconnected by an external signal, series type P-channel MOSFETs M3 and N are connected in parallel to the VCC side MOSFET M1 in the power supply voltage conversion circuit 1.
Channel MOSFET M4 is connected, and a MOSFET for resistance voltage division is connected to the connection node of M3 and M4.
Connect the gate terminal of Ml, MOSFET M3
, ~14, the test mode signal T is applied from the outside to the gate terminal.
Turn on by applying a signal inverted from EST by inverter 3.
It is supposed to be controlled off. On the other hand, MOSFET
M2 is always on by short-circuiting its gate and drain.

As a result, in the normal mode when the test mode signal TEST is set to low level, MOSFET M3
is turned off and M4 is turned on, so that P on the DC current bus
Turn on channel MOSFET Ml, MOSFET
The voltage at the node n1 obtained by dividing Vcc by the ratio of the on-resistances of ET M1 and M2 is supplied as a reference voltage Vref to the gate of the input differential transistor M14 of the impedance conversion circuit. In this embodiment, the MOSFET is set so that the reference voltage Vref is 3.3v.
Constants of Ml and M2 are set.

During the test mode in which the test mode signal TEST is set to high level, MOSFET M3 is turned on and MOSFET M4 is turned off, so that the gate voltage of M1 becomes VCC and the voltage of Ml
is turned off, and the DC current bus in the reference voltage generating circuit l is cut off.

Furthermore, the bias transistor M15 of the differential amplifier stage is also controlled by a signal obtained by inverting the test mode signal TEST using an inverter, and the bias transistor M15 is also controlled by a signal obtained by inverting the test mode signal TEST.
N-channel MOSFET M17 is connected between the gate terminal of Ml6 and the ground point, and the test mode signal T
It is designed to be turned on and off using EST. Also,
Output node n2 of the differential amplifier stage and the above output MOSFET
A transmission gate TG is connected between Ml6 and controlled by a test mode signal TEST and its inverted signal.

As a result, when the test mode signal TEST is at a low level, MOSFET M15 is turned on, MOSFET M17 is turned off, and the transmission gate TG is turned on, operating as a normal amplifier and supplying the voltage Vint at the same level as the reference voltage Vref to the internal circuit. . On the other hand, when the test mode signal TEST is at high level, MOSFET M
15 is turned off, the DC current bus of the differential amplifier stage is cut, and MOSFET 'Ml7 is turned on, so that the power MOSFET Ml6 is strongly turned on, and the external power supply voltage Vcc is supplied to the internal circuit. It becomes like this. In this case, the external voltage Vcc is set to 3.3V in the test mode. In addition, as shown in Figure 2, a Vcc' terminal is provided that is used only in the test mode.
If you connect it to the drain terminal of oSFET M16 and turn off M16 during test mode, you can use the Vcc' terminal to supply a low power supply voltage such as 3V to the internal circuit during test mode. Internal power supply voltage can be measured and checked externally in non-test mode.

Note that the capacitor Co connected to the output terminal n3 is for preventing oscillation and stabilizing the output voltage. MO which forms a pair with the input differential MOSFET Ml 4 from the output terminal n3
A feedback path F to SFET M13 is provided, and when the operating current of the internal circuit increases, the output MOS
When the level of node n2 rises to lower the resistance of FET M16 and the operating current of the internal circuit decreases, the MOS
The level of node n falls to increase the resistance of FET 116, which serves to keep Vint constant.

FIG. 3 shows an embodiment of a power supply voltage conversion circuit using an n-type silicon substrate.

In this embodiment, an N-channel MO constituting the internal circuit
A series type N-channel MOSFET Ml formed in a P-well region separated from the P-well region of the SFET.
', M2'' constitute a reference voltage generation circuit l.Moreover, MOSFETs M3' and M4'' in series are connected in parallel with MOSFET M2', and these MOSFETs M3' and M4' are connected to a test mode signal TSET. In the normal mode, MOSFET M2' is turned on to generate a reference voltage Vref such as 1.7V, which is obtained by dividing VCC by the on-resistance ratio with M3'. On the other hand, in test mode, M
It is configured to turn off the OSFET M2' and cut the DC current bus within the reference voltage generation circuit 1. The impedance conversion circuit 2 has an output MOSFE
T M16' is composed of an N-channel MOSFET, and its source terminal is connected to the ground point. Also,
A switch MOSFET M17' that is turned on and off by a test mode signal TSET is connected between the gate terminal of the output MOSFET M16' and the power supply voltage Vcc.

As a result, in the normal mode, the impedance conversion circuit 2 turns on the MOSFET M15 and turns off the MOSFET M17, so that the impedance conversion circuit 2 has a voltage of 1.7V corresponding to the reference voltage Vref.
A voltage like this is supplied to the internal circuit as a ground potential. On the other hand, in the test mode, MOSFET M15 is turned off to cut the DC current bus of the differential amplifier stage, and MOSFET M17' is turned on to cut the DC current bus of the differential amplifier stage.
Turn on SFETM16' strongly and connect the external ground potential (
Ov) is supplied to the internal circuit. Input differential MO
A feedback signal to the gate terminal of SFET M13 is directly applied from node n2.

In addition, in the embodiment shown in FIG. 1, the output MO in the test mode is
In order to make SFET Ml6 strongly on, MOSFET Ml7 connected to the ground point is turned on, so the load MOSFET of the differential amplifier stage
It is necessary to provide a transmission gate TG to eliminate the through current flowing through M12, but the second
In the illustrated embodiment, even if MOSFET M16'' is turned on, MOSFET M15 in the differential amplification stage is turned off and there is no path for through current to flow, so the transmission gate TG can be omitted.

FIG. 4 shows an embodiment of a power supply voltage conversion circuit in which the present invention is applied to a Bi-CMOS logic LSI.

In FIG. 4, 1a has three diodes Dl, D2,
A reference voltage generation circuit in which D3 and a bipolar transistor TI are connected in series; 2l is a reference voltage generation circuit 1;
A voltage Vi is driven by the reference voltage Vref generated by a, and is obtained by stepping down the power supply voltage ■cc by a predetermined level.
The output section 22 that generates nt is a feedback circuit that monitors the output voltage Vint and applies feedback to the transistor T1 in the reference voltage generation circuit la.

The output section 2l is composed of a MOSM 20 receiving a reference voltage Vref and Darlington-connected bibolar transistors T2 and T3 driven by the drain voltage of the MOSM 20.

The feedback circuit 22 is a pair of current mirror-connected P-type MOSFs whose source terminals are connected to output terminals n, .
ET M31. , M32, and transistors T4 and T5 connected between their drain terminals and ground.

In this embodiment, an N-type MOSFETM21 is provided in series with the diode array D1 to D3 in the reference voltage generating circuit la, and the TEST signal is sent to the inverter 3 during the test mode.
MOSFET M21 is turned off by the inverted signal, thereby making it possible to cut off the DC current bus of the reference voltage generation circuit 1a.

Further, the reference voltage Vr generated by the base voltage generation circuit 1a
An N-type MOSFET M22 is provided on the path that transmits ef to the MOSFET M20 of the output section 21, and in the test mode, the MOSFET M22 is turned on by an inverted signal of the TEST signal.
SFET M22 is turned off and the reference voltage generation circuit 1a
In addition to not transmitting the reference voltage Vref to M
Turn on OSFETM23 and MOSFET M20
The ground potential is applied instead of VrefO to the gate of . This allows MOSFET M20
is turned on more strongly than in normal mode, causing a transition. It functions to sufficiently turn on stars T2 and T3 and supply power supply voltage Vcc to the internal circuit.

Furthermore, in this embodiment, the MO of current mirror connection in the feedback circuit 22 that monitors the output voltage Vint is
- A P-type MOSFET M24 is installed between the gate terminals of SFETs M31 and M32 and the power supply voltage terminal Vcc, and an N-type MOSFET M is installed between the common gate terminal of MOSFETs M31 and M32 and the drain terminal of M31.
25 are connected to each other. MOSFET M2
4 and M25 are configured to be turned on and off in a complementary manner by the inverted signal of the TEST signal. In the test mode, MOSFET M24 is turned on and M25 is turned off, and M3 is connected to the gates of MOSFETs M31 and M32.
Applying vcc instead of the drain voltage of 1 turns them off. As a result, the DC current bus within the feedback circuit 22 is cut.

As explained above, in the above embodiment, the DC current bus in the power supply voltage conversion circuit is turned on and off by an external control signal.
Since a switch MOSFET that can be turned off is provided, during inspection, by turning off the MOSFET on the DC current bus in the power supply voltage conversion circuit using an external control signal, the current in the power supply voltage conversion circuit can be cut, thereby improving operation. It becomes possible to measure the standby current flowing through internal logic circuits and memory circuits when the device is stationary, which has the effect of improving LSI inspection efficiency and facilitating failure analysis.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the power supply voltage is supplied to the internal circuit through the power supply voltage conversion circuit even in the test mode, but the internal circuit is supplied not from the power supply voltage conversion circuit but from another power supply voltage terminal that is not used in the normal mode. The power supply voltage during the test mode may be supplied to the circuit.

The above description will mainly focus on the CMOS LS.
Although the present invention has been described as being applied to a power supply voltage conversion circuit in an I or Bi-CMOS LSIG, the present invention is not limited thereto and can be applied to semiconductor integrated circuits in general.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in an LSI that has an internal power supply voltage conversion circuit that steps down the external power supply voltage, product inspection and defect analysis can be easily performed by measuring the standby current.

[Brief explanation of drawings]

Figure 1 shows the present invention in a CMOS using P-type silicon as a substrate.
FIG. 2 is a circuit diagram showing a modification of the embodiment shown in FIG. 1. FIG. CMOS LS
FIG. 4 is a circuit diagram showing an embodiment in which the present invention is applied to a Bi-CMOS LST power supply voltage conversion circuit. 1, 1a... Reference voltage generation circuit, 2... Impedance conversion circuit, 2l... Power supply section, 22... Feedback circuit, Fig. 3 2 Fig. 4

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit device having a built-in power supply voltage conversion circuit that steps down the power supply voltage supplied from the outside and supplies it to an internal logic circuit, a DC current bus in the power supply voltage conversion circuit is provided. 1. A semiconductor integrated circuit device, comprising a switch means that can be turned on and off by an external control signal. 2. The semiconductor integrated circuit device according to claim 1, wherein the power supply voltage conversion circuit is comprised of a reference voltage generation section and an impedance conversion section having a feedback system. 3. The semiconductor integrated circuit device according to claim 1 or 2, further comprising a power supply voltage terminal to which an output section of the power supply voltage conversion circuit is connected, separate from the external power supply voltage terminal.