JPS5890750A - Preparation of lead frame - Google Patents

Preparation of lead frame

Info

Publication number
JPS5890750A
JPS5890750A JP19895982A JP19895982A JPS5890750A JP S5890750 A JPS5890750 A JP S5890750A JP 19895982 A JP19895982 A JP 19895982A JP 19895982 A JP19895982 A JP 19895982A JP S5890750 A JPS5890750 A JP S5890750A
Authority
JP
Japan
Prior art keywords
lead
tab
groove
frame
dam
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19895982A
Other languages
Japanese (ja)
Inventor
Akiro Hoshi
星 彰郎
Tomio Yamada
富男 山田
Seishiro Owaki
征四郎 大脇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP19895982A priority Critical patent/JPS5890750A/en
Publication of JPS5890750A publication Critical patent/JPS5890750A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842Mechanical treatment, e.g. punching, cutting, deforming, cold welding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To eliminate the pinch-off process by forming grooves through the press working for determined tab lead area of a thin and flat metal plate and thereafter forming the tab lead, dam lead and engaging area by the press working. CONSTITUTION:A specified lead frame unit is formed by punching a flat phosphor bronze plate in the thickness of about 0.25mm.. At this time, a groove is first formed in parallel to the vertical frame 8 on the one surface of a tab lead by the press working and thereafter a tab lead 1, dam lead 7, external lead 11, internal lead 12 and others are formed in the desired form by the continuous press working. Depth of groove may be about a half of the frame thickness. This groove is effective for decreasing deformation of tab lead. Next, semiconductor elements are bonded to the tab 6 and sealing is carried out in such a manner that the external edge of resin 2 is placed along the groove 13. Next, the tab lead 1 is cut from the vertical frame 8 of the groove 13 by the upper mold 14 and lower mold 15. Simultaneously unwanted part of dam lead 7 is also cut, and thereby the pinch-off process is eliminated.

Description

【発明の詳細な説明】 本発明は、レノンモールド型′半導体装置に用いられる
リードフレームの製法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a lead frame used in a Lennon mold type semiconductor device.

一般に半導体集積回路装置用リードフレームとして、半
導体素子を取り付けるタブリードを有するリードフレー
ムが広く用いられている。この種のリードフレームを用
いてレジンモールド型半導体装置を製造する場合、素子
をタブリードに取り付け、これをモールドしたあと、第
1図に示すように外観形状をよくするためタブリード1
をモールド部2から突出させないようにしてリード7し
一ム外枠から切り離す、いわゆるピンチオフと称する工
程が行なわれている。この場合先端を鋭利にした三角形
断面の一対の三角刃3をタブリードにくいこませてタブ
リードをリードフレームから切断分離している。
Generally, lead frames having tab leads for attaching semiconductor elements are widely used as lead frames for semiconductor integrated circuit devices. When manufacturing a resin-molded semiconductor device using this type of lead frame, after attaching the element to the tab lead and molding it, the tab lead 1 is attached to improve the external shape as shown in Figure 1.
A so-called pinch-off process is performed in which the lead 7 is separated from the outer frame without protruding from the mold part 2. In this case, a pair of triangular blades 3 with sharpened triangular sections are inserted into the tab lead to cut and separate the tab lead from the lead frame.

しかし、このようにして切断する場合、前記三角力の先
端は鋭利なため、すぐ摩耗してしまい、長時間の使用に
耐えられないものである。
However, when cutting in this manner, the tip of the triangular force is sharp, so it easily wears out and cannot withstand long-term use.

また、三角刃に位置ずれを生じると、モールド部に刃力
弓1つ掛かり、モールド部を破損させ耐湿性を低下させ
ることもある。
Furthermore, if the triangular blade is misaligned, the blade may become stuck on the mold part, damaging the mold part and reducing moisture resistance.

さらに、モールド外縁から離れた位置で切り込みを入れ
るとタブリードの切れ残二〇が生じ外観が損われる。こ
のようにビンチオ7エ程は多くの問題を有する作業であ
った。
Furthermore, if the cut is made at a position away from the outer edge of the mold, the tab lead will remain uncut and the appearance will be impaired. As described above, the Vincio 7 process was a work with many problems.

したがって、本発明は上記の問題を解決するためになさ
れたもので、その目的はビンチオ7エ程を廃止するため
のリードフレームの製法を提供することにある。
Therefore, the present invention has been made to solve the above problems, and its purpose is to provide a method for manufacturing a lead frame that eliminates the Vincio 7 process.

また、本発明の他の目的は半導体装置の外観不良を防止
するためのリードフレームの製法を提供することにある
Another object of the present invention is to provide a method for manufacturing a lead frame for preventing appearance defects of a semiconductor device.

さらにまた、本発明の他の目的は、モールドレノンのピ
ンチオフ作業による破損を防止するためのリードフレー
ムの製法を提供することにある。
Still another object of the present invention is to provide a method for manufacturing a lead frame that prevents damage to molded lenses due to pinch-off operations.

このような目的を達成するために本発明は、薄い平担な
金属板を用意し、その金属板のタブリードとなるべき一
部分にプレスにより溝を形成し、しかる後その金属板の
半導体素子を取り付けるタブ部を含むタブリード、グム
リード、連繋部ならびに池のリード部をプレスにより形
成することを特徴とするものである。以下図面により本
発明の詳細な説明する。
In order to achieve such an object, the present invention prepares a thin flat metal plate, forms a groove by pressing in a portion of the metal plate that is to become a tab lead, and then attaches a semiconductor element to the metal plate. It is characterized in that the tab lead including the tab part, the gum lead, the connecting part, and the pond lead part are formed by pressing. The present invention will be explained in detail below with reference to the drawings.

第2図は、本発明を実施して得られたリードフレームの
ユニットの一実施例を示す。同図において、リードフレ
ーム4は帯状の薄い(例えば厚さ0.25 +am)平
担なリン青銅板をプレスにより所望の形状に形成したも
ので枠状となっている。そして、この枠の中央には横方
向に伸びる細いタブリード、1か形成され、このタブリ
ード]の中央部には半導体素子5を取り付ける矩形のタ
ブ部6が形成されている。また、前記タブリード1に平
行に細長のダムリード7が形成され、タブリード1およ
びダムリード7の両端はそれぞれ縦枠8に一体的に連繋
されている。さらに、これらダムリード7と上枠9ある
いは下枠10との間に亘って外部リード11がほぼ等間
隔に7本設けられている。
FIG. 2 shows an example of a lead frame unit obtained by implementing the present invention. In the figure, a lead frame 4 is formed by pressing a thin flat phosphor bronze plate (for example, 0.25 mm thick) into a desired shape, and has a frame shape. A thin tab lead 1 extending laterally is formed in the center of this frame, and a rectangular tab portion 6 to which the semiconductor element 5 is attached is formed in the center of the tab lead. Further, an elongated dam lead 7 is formed parallel to the tab lead 1, and both ends of the tab lead 1 and the dam lead 7 are each integrally connected to a vertical frame 8. Furthermore, seven external leads 11 are provided at approximately equal intervals between the dam leads 7 and the upper frame 9 or the lower frame 10.

一方、前記外部リード11が一体的に連繋されているダ
ムリード7から前記タブ部6に向かってほぼ放射状に伸
びるようにそれぞれ内部リード12が形成される。また
、これら内部リード12の各先端部は他の内部リード1
2あるいはタブリード1およびタブ部4とは接しないよ
うに形成されている。
Meanwhile, inner leads 12 are formed to extend substantially radially toward the tab portion 6 from the dam lead 7 to which the outer leads 11 are integrally connected. Further, each tip of these internal leads 12 is connected to the other internal lead 1.
2 or the tab lead 1 and the tab portion 4 .

さらに、前記タブリード1の両端部における一表面には
縦枠8に平行に溝13が第2図で示すように形成されて
いる。前記溝13をプレスにより形成する場合、最初に
この溝をプレスにより形成し、そのあと連続的にプレス
して、所望形状のタブリード、グムリード、外部リード
、内部リード等を形成するようにする。これは溝を形成
するときに生しる歪を少なくし、タブリードの変形を小
さくするためである。このようにして形成する溝部の深
さはリードフレームの板厚の半分程度に形成することか
望ましい。
Furthermore, grooves 13 are formed in one surface of both ends of the tab lead 1 in parallel to the vertical frame 8, as shown in FIG. When the groove 13 is formed by pressing, the groove is first formed by pressing, and then pressed continuously to form tab leads, gum leads, external leads, internal leads, etc. of desired shapes. This is to reduce the distortion that occurs when forming the groove and to reduce the deformation of the tab lead. It is desirable that the depth of the groove formed in this manner be approximately half the thickness of the lead frame.

このようにして形成されたリードフレームのタブ部6に
半導体素子を金−シリコン共晶等の接着技術によって取
り付け、半導体素子の電極と内部リード12とをワイヤ
ボンディング技術により金またはアルミニウム等の金属
細線で接続する。
The semiconductor element is attached to the tab portion 6 of the lead frame formed in this way using an adhesion technique such as gold-silicon eutectic, and the electrodes of the semiconductor element and the internal leads 12 are connected using a wire bonding technique using thin metal wires such as gold or aluminum. Connect with.

次に、このようにリードフレームに組立てられた半導体
素子を保護するために、第2図および第3図の鎖線で示
すように、前記溝の部分までレジンでモールドする。す
なわち、タブリード1については前記溝13にモールド
レジン部2の外縁が沿うようにモールドする。
Next, in order to protect the semiconductor element assembled on the lead frame in this way, the grooves are molded with resin, as shown by the chain lines in FIGS. 2 and 3. That is, the tab lead 1 is molded so that the outer edge of the molded resin portion 2 is along the groove 13.

次に、モールドされたリードフレームから半導体装置を
完成品としてとり出すために、タブ17−ド1を前記溝
の部分で縦枠8からせん断すると同時に、ダムリード7
の不要部を切断する。この作業は第4図に示すような上
型14と下型15とからなる一対の切断型を使用してお
こなうことができる。下型13には半導体装置のモール
ドレジン部2を収容するような四部が形成されている。
Next, in order to take out the semiconductor device as a finished product from the molded lead frame, the tab 17-de 1 is sheared from the vertical frame 8 at the groove portion, and at the same time, the dam lead 7
Cut off unnecessary parts. This operation can be carried out using a pair of cutting dies consisting of an upper die 14 and a lower die 15 as shown in FIG. The lower mold 13 is formed with four parts that accommodate the mold resin part 2 of the semiconductor device.

この凹部にモールドレジン部2が入るように、かつ上枠
9および下枠10を、スプリング16を介して下型に支
持された平担な金属板17に密着させるようにしてモー
ルドの終了したリードフレームを下型にのせる。このよ
うにして前記リードフレームを下型にのせたあと、上型
を下降させる。上枠7および下枠8は下型の前記金属板
17と上型にスプリングを介して支持されている押え板
18とによりクランプされ、さらに上型を下降させると
、ダムリード7の不要部が上型と下型とに設けられた一
対の切断刃19により切断されると同時に、タブリード
1は上型に設けられた切断刃20により溝部18のとこ
ろで加圧されるために、核部において縦枠8からせん断
分離される。
The molded resin part 2 is placed in this recess, and the upper frame 9 and the lower frame 10 are brought into close contact with a flat metal plate 17 supported by the lower mold via a spring 16. Place the frame on the bottom mold. After the lead frame is placed on the lower die in this manner, the upper die is lowered. The upper frame 7 and the lower frame 8 are clamped by the metal plate 17 of the lower mold and a presser plate 18 supported by the upper mold via a spring, and when the upper mold is further lowered, the unnecessary part of the dam lead 7 is lifted up. At the same time that the tab lead 1 is cut by a pair of cutting blades 19 provided on the mold and the lower mold, the tab lead 1 is pressurized at the groove portion 18 by the cutting blade 20 provided on the upper mold, so that the vertical frame is cut at the core portion. It is shear separated from 8.

以上のように本発明によれば、従来のように先端の鋭利
な三角力を使用したピンチオフによる切断をなくするこ
とができるので、三角力の摩耗による作業能率の低下を
防ぐことがで外、特に大量に切断処理するさいに作業能
率が著しく改善されるという効果が得られる。また、タ
ブリードは、予めモールドレジン部外縁に沿うように形
成した溝部のところでせん断されることになるので、モ
ールドレジン部に切断万力91つ掛が9、モールドレノ
ン部を破損させ耐湿性を低下させることも防止できるの
で、完成品歩留が着しく向上する。また、タフリードの
切れ残りもなくなり、外観が損われるということもなく
なる。
As described above, according to the present invention, it is possible to eliminate pinch-off cutting using a triangular force with a sharp tip as in the past, so it is possible to prevent a decrease in work efficiency due to wear of the triangular force. Particularly when cutting a large amount of work, the effect of significantly improving work efficiency can be obtained. In addition, since the tab lead will be sheared at the groove part that has been formed in advance along the outer edge of the mold resin part, applying a cutting vise to the mold resin part will damage the mold resin part and reduce moisture resistance. Since it is also possible to prevent this from occurring, the yield of finished products is significantly improved. Furthermore, there will be no uncut parts of the tough lead, and the appearance will not be damaged.

なお、ダムリードの不要部が切断され、タブリードが縦
枠6からせん断された時点では、半導体装置は上枠およ
び下枠で支持されているので、次に別の切断成形型を使
用して上梓および下枠を切断すると同時に外部リード1
1を所定部分より折曲げて、完成された半導体装置とし
てとり出すことができる。
Note that when the unnecessary portion of the dam lead is cut off and the tab lead is sheared from the vertical frame 6, the semiconductor device is supported by the upper frame and the lower frame. External lead 1 is cut at the same time as cutting the bottom frame.
1 can be bent from a predetermined portion and taken out as a completed semiconductor device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のタブリードの切断を示す断面図。 第2図は本発明によるリードフレームの一実施例を示す
平面図、第3図は第2図A−A’線に沿う断面を示す断
面図、第4図は本発明によるタブリードのせん断および
ダムリードの不要部切断の一実施例を示す断面図である
。 1−一一一タブリード、2−−−−モールドレジン部。 3−一一一三角刃、4−−−−リードフレーム、5−−
−一半導体素子、6−−−−タブ部、7−−−−ダムリ
ード、8−−一一縦枠、9−−−−上枠、10−−−一
下枠、11−−−−外部リード、12−−−一内部す−
ド、13−−−−溝。 14−−−一切断型(上型)、15−−−一切断型(下
型)f16−−−−スプリング、17−−−−金属板、
18−−−−押え板、19−−−一切断刀、20−−−
−切断刀。 第  2  図 第  3 図 第  4 図 / /1 /Z
FIG. 1 is a sectional view showing the cutting of a conventional tab lead. FIG. 2 is a plan view showing an embodiment of a lead frame according to the present invention, FIG. 3 is a cross-sectional view taken along the line A-A' in FIG. 2, and FIG. 4 is a sheared tab lead and a dam lead according to the present invention. FIG. 2 is a cross-sectional view showing an example of cutting off unnecessary parts of the image forming apparatus. 1-111 tab lead, 2---- mold resin part. 3-11 triangular blade, 4--lead frame, 5--
-1 semiconductor element, 6---Tab part, 7---Dam lead, 8---11 vertical frame, 9---upper frame, 10---1 lower frame, 11---external lead , 12---Ichiuchisu-
Do, 13---groove. 14---One-cut type (upper type), 15---One-cut type (lower type) f16---Spring, 17---Metal plate,
18---- Pressing plate, 19--- Cutting knife, 20---
- Cutting knife. Figure 2 Figure 3 Figure 4 / /1 /Z

Claims (1)

【特許請求の範囲】[Claims] 薄い平担な金属板を用意し、その金属板のタブリードと
なるべき一部分にプレスにより溝を形成し、しかる後そ
の金属板の半導体素子を取り付けるタブ部を含むタブリ
ード、ダムリード、連繋部ならびに池のリード部をプレ
スにより形成することを特徴とする。リードフレームの
製法。
A thin flat metal plate is prepared, a groove is formed by pressing in a part of the metal plate that is to become a tab lead, and then the tab lead, dam lead, connecting part, and pond including the tab part where the semiconductor element is attached to the metal plate are formed. A feature is that the lead portion is formed by pressing. Lead frame manufacturing method.
JP19895982A 1982-11-15 1982-11-15 Preparation of lead frame Pending JPS5890750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19895982A JPS5890750A (en) 1982-11-15 1982-11-15 Preparation of lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19895982A JPS5890750A (en) 1982-11-15 1982-11-15 Preparation of lead frame

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP5858775A Division JPS51134569A (en) 1975-05-19 1975-05-19 Semiconductor unit manufacturing process, lead frame used in the semi- conductor and its manufacturing process

Publications (1)

Publication Number Publication Date
JPS5890750A true JPS5890750A (en) 1983-05-30

Family

ID=16399777

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19895982A Pending JPS5890750A (en) 1982-11-15 1982-11-15 Preparation of lead frame

Country Status (1)

Country Link
JP (1) JPS5890750A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1017215C2 (en) * 2001-01-29 2002-07-30 Fico Bv Carrier part from carrier removing apparatus and method involves arranging notched line in carrier on at least one side of carrier along part of length of separating edge prior to performing separating operation
WO2002061822A1 (en) 2001-01-29 2002-08-08 Fico B.V. Method and apparatus for removing a carrier part from a carrier, and a product removed from a carrier

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5037362A (en) * 1973-08-06 1975-04-08

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5037362A (en) * 1973-08-06 1975-04-08

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1017215C2 (en) * 2001-01-29 2002-07-30 Fico Bv Carrier part from carrier removing apparatus and method involves arranging notched line in carrier on at least one side of carrier along part of length of separating edge prior to performing separating operation
WO2002061822A1 (en) 2001-01-29 2002-08-08 Fico B.V. Method and apparatus for removing a carrier part from a carrier, and a product removed from a carrier
US7162906B2 (en) 2001-01-29 2007-01-16 Fico B.V. Method and apparatus for removing a carrier part from a carrier

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