JPS5890184A - Testing device for circuit - Google Patents

Abstract

PURPOSE:To enable an efficient circuit test in a short time, to reduce processes for inspecting IC, and thereby to improve the rate of operation, by inputting a multivalue level signal once in a liquid-crystal driving circuit, etc. CONSTITUTION:A multivalue level signal SIG forms a pattern set beforehand while varying its level among four values, for instance, in each period, and takes a specified level in a period Tn. After the signal SIG becomes stables in the period Tn, FF1 and FF2 are reset by a strobe signal ST, an analog switch ASWi is made to be continuous by each output Q, and an upper limit value is impressed sequentially on a comparator C1 from a voltage source VHi, while a lower limit value is impressed sequentially on a comparator C2 from a voltage source VLi. Then, reference patterns REF1 and REF2 which are inputted in exclusive OR circuits EX1 and EX2 are switched at every fall of a signal STi, and an output of each circuit EX is delivered outside via an OR gate OR and an AND gate AND.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit testing device, and in particular, to a circuit testing device suitable for testing integrated circuits that output multiple types of levels or multiple levels for applications such as liquid crystal displays. It is on offer.

In general, electronic, electronic type circuits that have the function of outputting for liquid crystal displays, T, 8I (large-scale integrated circuits) for watches, etc.
In many cases, the liquid crystal drive output is not a binary level of "1" or "0", but a multiple level, that is, a multivalue level.

From this loose circuit, Vl, V2. V3. The four levels of back pressure at V4 are TI, T2. T3...... is output in a predetermined pattern for each period. Determining whether or not such a multilevel signal is always output by the IE
In other words, for circuit testing, VI V2. V3. V4
It is necessary to determine whether or not each level of V1.
V2. V3. V4 is each upper limit mVQH1°VOI
2. VOI3. VOI4 and lower limit VOLI, VO
L2゜VOL3. It is necessary to check whether it is between VOL4 or not.

FIG. 2 is a partial block diagram of a circuit testing device constructed from this point of view.
A multi-level signal S as shown in a) is inputted, and the inverted input has each level Vl, V2 . V3. V4
(Upper limit @'1M that outputs the D upper limit value.

Comparator, CZVi, inputted with 111 levels of source VH
A multilevel signal BIG is input to its non-inverting input, and each level Ml, V2 . V3゜v
A comparator which outputs the lower limit value of 4 and inputs the output level of the source VL, ]fiX1 inputs the LLl power of the regulator C1 and the reference pattern REFI, and is an exclusive!16 PI sum circuit. (Excurmbu or Kate), B
Output of I2 comparator C2 and reference pattern RFiF
2 is input to the exclusive OR circuit (exclunbuoragut), OR is input to each exclusive OR circuit (exclunbuoragut) FiX1.
An OR gate that receives the output signal of BI2, AND is a logic type circuit that outputs the logical product of the output of the strobe T and OR as shown in Figure 1 (b'). 0 In such a configuration, EXCLUMB OR GATE EX1. ．． BI3 ke comparator (
! 1.02 output and reference pattern R1'F1, R11
! i? If there is a mismatch between R1X1. Either FiX2 is 11
” is output, ``1'' is output from OR.

The circuit test is for each level 'l, V2. V3. This is done every V4, and first the output level of the source VH is set to the upper limit value 115.
After setting the output level of OHI and lower limit power supply VL to VOLl, TI, T2. For each period of T3......, the reference pattern R11iF1, RE? 2 first
As shown in Figures (o) and (a), the multilevel signal S and G are input while changing. As a result, the multi-level signal B
The V rubel of engineering G is the upper limit VOHI and the lower limit VO'L1
Exclusive or game if between) BXI, F
The output of iX2 is rOJ throughout the entire period f, so no signal is output from either the OR gate OR or the AND gate, and it can be determined that the level v1 is normal.

Next, the output level of the upper limit power supply VH is set to VOH2, and the output level of the lower limit power supply VT is set to VOL2. T3......... put the butter yRKFI, RIF'2 for each intercostal space i-th BI1(s)
, while changing the multi-level signal 8 as shown in (f).
Enter engineering G. As a result, v of the multilevel signal S
Level 2 is between the upper limit VOH2 and the lower limit @VOL2 (that is exclusive or game) I! iX1. u
The output of x2 is "0" throughout the entire period, so no signal is output from either the OR gate OR or the AND gate AN'D? It is possible to determine that level v2 is normal.

Next, after setting the upper limit voltage and the output level of the source VH to VOH3, and setting the lower limit voltage and the output level of the source VL to VOH3, TI, T2. Standard turn R1 for each u-opened can of T3...! iII'l, FjE11
In the first picture of F2, input the multi-value level No. 41 SIG while changing as shown in Figure 1, and perform the same test.The output level of the upper limit value is set to VOI4, the output level of the source VH is set to VOI4, and the lower limit value is set to VOI4. The output level of the source VL is set to VOI, 4, and above, T1. , T2. For each period of T3......, the reference patterns RIIIFI and RtIiF2 are changed as shown in Fig. 1 (g) and (b). Perform the same test.

As a result of conducting the test as described above, the multi-level level belief @
Each level of s■e V1. V2. V3. If all V4s are within their respective tolerance ranges, then the test is complete throughout the test period) 1! iX1. ] DX2 does not output a "1" signal, and OAGOO FOR also does not output a signal.

However, in reality, the delay time of the comparators Oi and 02, the settling time when the level of the multi-level signal S and G changes, etc., and the delay time of each period JIT1. T2゜T3...
. . . change from 1j to OR gate) OR often outputs a false signal. For this reason, OR gate O
The output signal of R is passed through an AND gate (ANT) to the +1. ! r
[Before #:j] output is regulated. In other words, only the necessary value IfLti is output in the evening 1 part by the 111 force 1s t+ p coslope damage number day T of the OR gate OR.

This strobe signal is expected to have a settling time of 1 after the multi-value level signal @SIG changes, as well as the response time of the comparator 01.02, Exclump ORG (FJI, l1liX2, OR gate OR, etc.). It is set at a time that takes into account ff1, and T1. T2. It is common practice to output twice in each period of T3. This is to determine whether or not the difference is within the range of 7.3 degrees. Now, during the test period of the level v2 of the multi-f1u level signal BIG, during the period T6, the multi-level signal STG is within the 11th fl ( As shown by the dotted line in a), the upper limit level VOH
2'(z), the output of the comparator L/-1 becomes "1", which causes a difference with the reference pattern REFI shown in FIG. KXI, T6 from ORGATE OR
During the period, a "1" signal is output as shown in FIG. 1 Qcl, so a fail pulse is output from AND as shown in FIG. 1 (top).

Therefore, by monitoring the output of the AND, it is determined that a level failure has occurred.

On the other hand, in the test period of level 2 of the multi-level signal BIG, during the period T8...], the multi-level signal BIG is at the first level.
As shown by the dotted line in Figure (a), if the time it takes to reach the required level v2 is 17, then the output of the comparator 02 is ``17'' until the multilevel signal @SG reaches the lower limit value VOT, 2. 1'', and during this period, a difference occurs between the reference pattern IF2 shown in FIG. 1(f) VC.
ij: Since a "1" signal is output as shown in FIG. 1 (k) during the T8 period, the first
As shown in Figure (1), 7 A4 pulses are output. Therefore, by monitoring the output of the AND gate, it is possible to determine whether a level failure has occurred. However, as is clear from the above explanation, conventional circuit testing equipment Signal S engineering G
Each level Vl, V2. V3. In order to judge whether or not V4 is normal, the multi-level signal BNG with the same output waveform is input four times, and each time the upper limit power supply VH1 lower limit 1
1, and input the corresponding reference patterns RIliF'l and REF2, respectively, which inevitably lengthens the test time. Moreover, multi-value level example number 8 G
As the output time for one time becomes longer, the tiIt test time also increases with kneading, so a decrease in test efficiency was inevitable.

Therefore, the object of the present invention is to overcome the drawbacks of the prior art described above (L,
It is an object of the present invention to provide a circuit testing device which enables efficient testing in a short time by inputting a multilevel signal only once and determining pass/fail for all levels.

In order to achieve the above objective f, the present invention provides a circuit testing device for multiple periods of 4! ! a comparison means inputted with a multilevel signal that takes one level among the plurality of levels during j period;
Reference means for sequentially inputting tolerance levels corresponding to all of the plurality of levels within each 1111 period into the comparison means in a time-sharing manner, and outputting the comparison means according to the level that the multilevel signal should take in each period. and a determination means for determining the pattern.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a partial block diagram of a circuit testing apparatus according to an embodiment of the present invention, in which VT, l, VT, 2. VL3゜v
L4N' multi-value level signal and each level of SIG VLV2V3
．． Lower limit f4 of V4 V OL 1, V OL 2,
V OT+: Voltage source that generates VOL4, V
HI, VH2, VH3, VH4 (each level of 4-valued bell signal BIG Vl, V2. Upper limit value of V3゜■4 Voltage source to generate VOHI, VOH2, VOH3, VOH4'lr, AEIWl, ASW2.ASW3)
lol.

Four voltage sources VLI, VL2. VL3. Lower limit 111j occurring at VT, 4 VOL l , VOL2 , V
OL3, VOL4 f, selectively comparator C2
An analog switch connected to the inverting input of A8W5. A
SW6. ASW7. ASW8 is Denshobara VHI, VH2
, VH3, VH4 upper limit value VOI (1, VOH
2, VOH3, VOH4e selectively connected to the inverting type nof of comparator C1 analog switch f, D I H
D2 is a delay line that delays the first strobe signal STI by delaying the o -y' signal s T f - +4i JITa, and delays the first strobe signal S'rl received via the buffer Ble by a certain time Td. The delay line D generates the second strobe signal 5T2y.
3 is a delay line which receives the fc second strobe signal via the buffer B2i and delays it by a fixed time '14 and then generates the third strobe signal S'f'3, and D4 receives it via the buffer B3. The third strobe signal
A delay line that generates the hanging 4 strobe buoy No. 1 sT4 with a delay of
．． D3. 1st from D4. Mulberry 2. Third. 4th strobe master STI, ST2. ST3. The NOR gate that outputs the NOR condition of ST4, Nφ, inverts the output of the NOR gate NOH.
Fi.

F1'2 r, t A D-type flip-flop MA that is directly reset by the strobe signal BT and operates using the signal from the NOR gate LLOR as the clock signal.
NANZ receives the Q output of flip-flop FFI, the available output of flip-flop FF2, the available output of N1 flip-flop IrF1, and the available output of flip-flop FB'2. NAN4 is a NAND gate receiving Q output, NAN4 is a NAND gate receiving each Q output of flip-flops FFI and FF2), and IJAN5 is NAND gate NAN2.

Receives the output of NAN3 and sends the output to flipflora 7'
Nantes gate, INI, which is used as the D input of FF2.

Engineering N2, Engineering N3, IN4 are Nantes Gate NANI, NA
The outputs of N2, NAN3, and NAN4 are inverted and output to analog switches Asw1, ABN5, and ASW2, respectively.
and ABN6. A. BN2 and ASW7, Musw4 and 18
This is an inverter for controlling W8. Note that since the enable output of the flip-flop FFI is connected to the D input, the states of its Q output and enable output are inverted in synchronization with each rising edge of the clock input.

The operation of the configuration as described above will now be explained according to the flowchart shown in FIG. By the way, Figure 4 F
This is a waveform diagram of each part of the configuration shown in FIG. 3, and shows only one period Tn in which the multi-level signal Xa is at one level.

Figure (a) shows the upper limit values VOHI and VOH during period Tn.
2.

VOH3, VOH4, lower limit value VOLI, VOL2
．． Waveform diagram of VOIJ3 VOL4, (b) is strobe signal, (C).

(d) are flip-flops FF1. FF2
Each Q, output, (θ), (r), (g), (h)
are the first. Second.

3rd and 4th straw buoy i@8T1, ST21T3.

8T4. (1) is the signal from the inverter Nφ given to the AND gate ANI), which is a 7-lip 70-tube FFI
.

Inverted waveform of the clock signal given to FF2, (j).

(1), (n), (p) are the standard butter y
Input example of RFfF1, (k)6n), (o), (q
) are input examples of the reference pattern RB'F2.

Now, as shown in FIG. 1(a), the multi-level signal 8G has its level Vl, V2, V3,
During each period, for example, during the Tn period, the multilevel signal S and G take a predetermined pattern while changing between V4 and V4 as shown in FIG.
, V2, V3, or V4 and does not change.

After entering the Tn period, after waiting for the multilevel signal S to become stable, when the strobe signal BT is input at the timing shown in FIG. 4(b), the flip-flops FFI,
FF2 is reset and each Q.

Since the output is set to "0", the output of the NAND game) NANI becomes rOJ, and the output of the inverter N1 becomes rlJ. For this reason, Analog Suitsuna ASW1, ABN5
conducts and the back pressure source VHI is applied to the inverting input of comparator C1.
The upper limit value VOHI is input to the inverting input of the comparator 02, and the lower limit lIIVOL1 is input from the voltage and Shobara V'LI to the inverting input of the comparator 02, respectively.

On the other hand, the strobe signal 8T is input to the delay line D1, and after a certain period of time Td has elapsed, a first strobe signal 8T1 is generated as shown in FIG. 4(e). This first strobe signal Tli is input to the AND gate A'NT) via the NOR gate NOR and the inverter INφ, and the first strobe signal STI
” to connect to the outside world.

The first strobe signal day T1 is 7 ribs via NOR 'FFI, ]ll'? 2 becomes the clock input, and as the clock falls, only the state of the flip-flop FFI 'fr changes as shown in FIG. 4(a).

As a result, the output of the Nant gate NANI becomes "1" and the output of the Nant gate NAN2 becomes "0", so the output of the inverter IN2 becomes "1" instead of the inverter Nl.
” 5. Therefore, the analog switch A8W2. A
l3W6 becomes conductive, and the upper limit value VOH2 is input from the voltage source VH2 to the inverting input of the comparator 01, and the lower limit value VOT,2 is input from the voltage source VL2 to the inverting input of the comparator C2.

On the other hand, the first strobe signal T1 is input to the delay line D2 via the buffer B1, and the second strobe signal T1 is input to the delay line D2 for a certain period of time T (after l has elapsed, ω in FIG. 4).
2 occurs. This second strobe signal @5T2i1 is connected via the NOR gate NOR and the inverter Nφ.
1・AND K is input, and the output of the OR gate OR is sent to the second
Connected to the outside while the strobe signal ST2 is "1".

The second strobe signal T2 is passed through the flip-flop FF1. It becomes the clock input of FF2, and as the clock falls, the flip-flops FFI and 7F2
4(c) and (a). This means that the D input of the flip 70 block IFF2 is connected to the NAND gate IJAN2. This is because it was ``1'' through NAIJ5. As a result, the output of NAND game (NAM3) becomes "1", and the output of NAND game (NAM3) becomes "1".
Therefore, the output of inverter N3 becomes "1" instead of inverter N2.

For this reason, the analog switch A8W3. A13W7 becomes conductive, and the upper limit value VOH3 is input from the voltage source V1 (3) to the inverting input of the comparator C1, and the lower limit value VOL3 is input from the voltage source VT, 3 to the inverting input of the comparator 02.

On the other hand, the second strobe signal @s'r2 is input to the delay line D3 via the buffer B2, and after a certain period of time T (1) has elapsed, a third strobe signal 8T3 as shown in FIG. 4(g) is generated. This third strobe signal 8T3 is input to the AND gate AND via the NOR gate NOR and the inverter Nφ, and the output of the OR gate OR is connected to the outside while the third strobe signal 8T3 is “1”.

The third strobe bias @EIT3 becomes the clock input of the 7-lip 70-tube F'FI and FF2 via the NOR gate, and as it falls, the flip-flop?? '
The state of F1 is changed as shown in FIG. 4(C). The reason why the Q output of the flip-flop FF2 remains "1" is because the D input of the flip 70 tube II'F2 is connected to the Nant gate NAN3. This is because it was "1" through MAM5. As a result, the output of NAN3 (Nandogoo) is “1”.
'', and the output of NAN4 becomes "0", so the output of inverter N4 becomes "1" instead of inverter N3. For this reason, analog switch A8W
4. The upper limit value VOH4 is applied to the inverting input of the comparator o1 from the voltage source VH4, and the upper limit value VOH4 is applied to the inverting input of the comparator o1.
The lower limit (iiVOL4) is inputted from the voltage source VL4 to the inverting input of the voltage source VL4.

On the other hand, the third strobe signal T3 is input to the delay line D3 via the buffer B3, and after a certain period of time Ta has elapsed, the fourth strobe signal 8T is input as shown in FIG.
4 occurs. This fourth strobe signal ST4 is input to the AND gate AND through the inverter Nφ, and the output of the OR gate OR is connected to the outside while the fourth strobe signal θT4 is [1,''.

The fourth strobe signal EIT4 is a 7-rip 70-rip 'FF1. It becomes the clock power of FF2 and sets the Q output of both flip-flops FFI and FF2 to "0". As a result, the output of the NAND gate NAN4 becomes "1" and the output of the NAND gate NANI becomes rOJ, so the output of the inverter N1 becomes "1" again.
]”, and the analog switch A8W1. This will make A8W5 conductive.

Through the above operations, the comparator C1 has 125 pressure sources VHI, VH2,'l+3. 'From VH4 to upper limit VOH
I.

VOH2, VOH3, VC)H4 are applied sequentially, and the voltage sources VLI, VL are applied to the comparator C2.
2.

VL3. VT, 4 to lower limit 111iVOLl, VO
L2. Since VOT and 3°VOL4 are applied +1Ifj times, all the upper limits (fi, lower 1i[) are input to each comparator (11, 02) during the period TiO, as shown in FIG. 4(a). This will result in n.

On the other hand, Excle 7 Poor Gate ff1Xl, Ti1
Reference pattern RKFI RLFZ input to X2 1st, 2nd. Third. Fourth strobe signal STI, BT2
゜8T3. It switches every time ST4 falls,
Is the change in response to the desired level pC of the multi-level signal S1G during the period Tn? 0, that is, in period Tn, many 1
When the 1ti level signal SIG should be at level v1,
The reference patterns RIIIFI and RF2 change as shown in FIG.
iF1 and RIF2 are each 7'1. Figure 4 (1),
(Changes as shown on the screen. 4. When the 4-value level signal @srG should be at level ■3, the reference pattern REFI, REF
2 changes as shown in the 41st lines I(n) and (o), respectively. When the multi-level signal θH3 should be at level v4, the reference patterns R edition Fl and RKF2 change as shown in the 41st lines I(n) and (o), respectively. ) and (q). Although the actual circuits for generating the reference patterns REFI and REF2 are not shown here, the flips 7rr and FF1 . ,
FF2's tb force and each rule 1 interval Tn'! Input the data to specify r% as the address and E2.

By using the ROM1i, it can be easily constructed.

Through the above-described operation, the circuit test drive is performed when the multi-level signal S is at the level Vl v2. For every period Tn in which tL of Va, V4 is at one level, all upper limits D
fvon1. von2. vona, voH4 and all lower limits 1jhVOLl, VOL2. VOL3. VOL4
It is possible to carry out a comparative test of and multi-level L/H/L/Daigo S-G. For example, if the multi-level signal S is at level v2 during period Tn, first the upper limit value V
Comparison with OHI and lower limit value VOLI is made by the comparator (31
, 02. At this time, since the multilevel signal BIG is smaller than the (7) ratio M value, each comparator
The output of 1°o2 is rOJ, and (r
Etascomb OR circuits FiX1.n) receiving inputs from reference patterns RKFI and RFtF2 as shown in FIG.
BI3 outputs "0". For this reason, ORKATE OR
The output of is also rOJ, and no signal is output from the AND gate AND which outputs the output of OR (OR) together with the first strobe signal BT1 to the outside. Next, as the first strobe number 8T1 falls, the comparators a1 and a
The upper limit value VOH2 and the lower limit value 'VOL2 are input to 2. At this time, if the level 2 of the multilevel level signal EIIG is normal, the output of the comparator C1 is "0" and the output of the comparator C2 is "1". becomes.

At this time, since the reference pattern RKFl is "0" and RFiF2 is "1", Exclump or Agut PXI,
FfX2 ij: r Execute all OJ outputs. For this reason,
The output of the OR gate OR is also "0", and no signal is output from the AND gate AND which outputs the output of the OR gate to the outside together with the second strobe signal 8T2. Next, when the second strobe signal 8T2 falls, the comparator ol, c2 has an upper limit value VOH3° and a lower limit value VOI, 3°.
is input, but at this time, the output of the comparator Of, a2 becomes "l". At this time, Ik quasi-pattern R1nF1
, RTiF2 are both set to "1", so Exklump or Agut BX1. PI3 sends rOJ output tt3 0 Therefore, the output of OR gate OR is also "0"
, and along with the third strobe signal ST3, O
No signal is output from the AND gate A1JD which outputs the output of R to the outside. .

Next, as the third strobe signal @8T3 falls, comparators 01 and 02VC set the upper limit value VOH4 and the lower limit value V O
T, 4 is input, but at this time comparator 01゜0
The output of 2 becomes "1". At this time, the standard (turn R)
Since both nF1 and REF2 are "1", Excl 7 Poor Agut 11! Xi, FtX2 is “0
” output. Therefore, the output of the OR gate OR is also rO
J, and along with the fourth strobe signal BT4,
No signal is output from the AND gate AND which outputs the output of the OR to the outside. In other words, since no signal is output from AND during the Tn period, it can be determined that the multi-level signal BIG during this period was normally output.In contrast, FIG.
Suppose that the settling time at the level V2t of the multi-value level 118TG is too long as shown in FIG. In this case, the comparator cl and o2 have an upper limit VOH2 and a lower limit f
When direct VOL2 is applied, comparators 01,0
At this time, the reference patterns REFI and REF2 are respectively rOJ and rlJ, and an output of "1" is sent from Excurmbu or Agut BX2, and the output of the OR gate OR. is set to "1".

For this reason, the second strike C for ANDG -)AND
At the time when the 1-p signal ST2 is applied, the AND gate A
A "1" output is sent from the ND, and a circuit abnormality is outputted to the external phase 5.

For example, IJ is shown when the multilevel signal 8G is at level V2 during t, J1, period 11JI T n, but other levels Vl, V3. When taking V4, the circuit test can be performed in the same way.

Note that the delay line DI, D2. D3. D4
The delay time T() is given by Kamepressure Shobara HI, VH2,
VH3゜Vl14 and Vl,l,VT,2,Vl3
, the time it takes for Ichikawa to stabilize after switching off Vl4 is set in A7. Then, excursion gate IXI is executed until each upper limit (it) and lower limit value are stabilized.

The error signal output by EX2 is the first. Second. Third. Fourth strobe signal 8T1. ST2. It is regulated by the AND gate AND receiving ST3.8T4 and is not output to the outside.

In the configuration as shown in FIG. 3, the multi-level signal Nikko G is connected to the interval T1. T2. T3...... Different level for each V1. V2. V3. Even when testing a circuit that produces an output such as V4, the multi-level signal Nikko G only needs to be input once and then judged as correct or incorrect for all levels. I stutter.

In addition, in the above embodiment, comparator 01.02
Upper limit value VOHI, VOH2, VOH3, VOH
4 and lower limit values VO'L1, VOL2. VOL3
゜VOL4 is set to a dedicated voltage ([VHl, VH2
, VH3°VH4, VLl, Vl2. Vl3. V
14 is used as an example, but as shown in the block diagram of FIG. 5, flip-flops FFI, ? 1
Unique element ROMI whose address is input with the output of 1'2
, ROM2 is used to digitally output the necessary upper and lower limit values at the necessary timing, and these are converted to analog traces via kD/Af converters DAI and DA2, and then given to each comparator al, o2. It is also possible to have a configuration like this.

Furthermore, in the above embodiment, the case where two comparators C1 to which the upper limit value is input and the comparator 02 to which the lower limit value is input is shown as ff1J, but the implementation of the present invention is limited to this. Not things.

VOHI upper limit value and lower limit value in one comparator.

VOLI, VOH2, VOL2, 'VOHa
, VOL3. Input them in the order of VOH4゜VOL4, and accordingly, the level of the multi-level signal 8G, ■I,
V2. V3. By inputting the necessary reference pattern set according to V4 at the same time, the purpose can be achieved with a simpler circuit configuration.

Further, the present invention can effectively deal with not only the case where the multilevel signal 81G has four levels but also the case where it takes other numbers of levels based on the same idea.

Furthermore, the present invention can be applied not only to liquid crystal drive circuits but also to other types of multi-level output circuits.
This can be widely applied to improve the efficiency of circuit tests.

As described above, according to the present invention, the circuit M, which conventionally had to repeatedly input a multi-level signal of the same pattern while switching the upper limit value and lower limit value, can be replaced with a multi-level signal input once. 131 that can be implemented just by inputting!
Therefore, it is possible to perform 5tjJ18 tests efficiently in a short time, and it is also possible to shorten the inspection process of the beam structure circuit and improve the operation rate. You can see the soap dispenser for yourself.

[Brief explanation of the drawing]

Fig. 1 is a time chart showing a conventional multi-level signal testing method, and Fig. 2 is a partial block of a conventional circuit test device.
! Figure 3 is a partial block of a circuit testing device according to an embodiment of the present invention. FIG. 7 is a partial block diagram of a circuit 1liIl' test device according to another example; Ql, 02 ・) 7 valet, VH, VT,, VHI,
VH2, VH3, VH4, VLI, VL2. VL3. V
L4 Wlf source, ASWl, A8W2. Mu8Wa,
A8W4. ASW5゜ASW6. A8W7. A
8W8...Analog switch, FFI, FIF
2...Flip 70 knob, DI, D2°D3. D
4...Delay line. Applicant's agent Kiyoshi Katsumata (1) Figure (b)

Claims (1)

[Scope of Claims] 1. Comparison means that receives a multilevel signal that takes one level among a plurality of levels in each of a plurality of periods;
A reference means for sequentially inputting the allowable levels for all of the plurality of levels in each period into the comparison means in a time-sharing manner, and a reference means for inputting the output pattern of the comparison means in accordance with the level that the multilevel signal should take in each period. A circuit testing device 2 characterized in that it comprises a judgment means for making a judgment, in claim 1, the judgment means compares a reference pattern prepared for each of a plurality of levels and an output pattern of the comparison means. A circuit testing device characterized by comprising a circuit for comparison. 3. The circuit according to claim 1, characterized in that the reference means consists of a voltage source for generating a plurality of tolerance levels and an analog switch electrodepositically connected to the comparison means. Test equipment. 4. A circuit testing device according to claim 3, characterized in that the voltage source comprises a D/A converter that generates a desired voltage by digital input.