JPS588775B2 - Pulse interval detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse interval detection method for determining the length of an input pulse interval with respect to a standard time by comparing the input pulse interval with a standard time.

Conventionally, to measure the interval between pulses, the number of pulses of a reference pulse generator included between adjacent pulses to be measured is counted using a counter and a gate that opens and closes depending on the pulse to be measured, or the number of pulses from a reference pulse generator included between adjacent pulses to be measured is measured. A method of determining the length of the pulse interval by superimposing seven measured pulses using a periodic pulse generator and comparing them was used.

However, all of these methods have the disadvantage of requiring relatively large-scale circuits for measurement.

The present invention does not have the drawbacks of the prior art methods and can accurately measure pulse intervals with an extremely simple circuit configuration.

The present invention will be explained in detail below based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the pulse interval detection method of the present invention.

In the figure, 11 is a pulse oscillator, 2 is a programmable counter, 3 is a count control section, 4 is a human input terminal for the pulse to be measured, 5 and 7 are inverters, 6 is a delay circuit, 8 and 11
1 is a set/reset flip-flop (hereinafter abbreviated as F.F.), 9 and 10 are NAND gates, and 12 is an external output terminal.

In addition, Figure 2 shows a human capsule, and in the figure t
1(s) indicates the pulse width, and T(S) indicates the pulse interval.

It is assumed that the pulse width t1 is as short as possible to the extent that the digital device in this embodiment can operate.

For example, the pulse width t1 is about 100 ns.

Now, when a human pulse as shown in FIG. 2 is input to the pulse input terminal 4, the input pulse is inverted by the inverter 5 and then applied to the input terminals A of F and FB via the delay circuit 6.

That is, "1" is always applied to the terminal A, and it becomes "0" only when the input pulse force is cut off.

The output pulse of the delay circuit 6 is simultaneously applied to the clear terminal CL of the programmable counter 2, and the counter 2 is cleared with its "0".

Therefore, the counter 2 is cleared regardless of the state at that time, and the output terminal CA becomes "0", so the output of the inverter 7 becomes "1", and this becomes the F. It is applied to input terminal B of F8.

For F, F8 and F, F11, when one input terminal is "1" and the other manual terminal is "0", the output terminal corresponding to the input terminal that is "0" is "1", and the output of the other terminal is "1". The terminal is “
0", and the previous output state is maintained with both input terminals set to "1".

Therefore, F and F8 maintain "1" at the output terminal C and "0" at the output terminal D in this state.

That is, F. F8 is set to this state every time an input pulse arrives and stores this state.

The programmable counter 2 starts counting the reference pulses from the pulse oscillator 1 again from the state cleared by the input pulse as described above.If the count number set to the counter 2 from the count control section 3 is N, the counter 2 When N counts are completed, a carryout "1" is output to the output terminal CA.

Therefore, when the oscillation frequency of the pulse oscillator is f (HZ), the counter 2 outputs "1" to the output terminal CA N/f (S) after being cleared.

However, the time N/f(S) is the period T(
If it is longer than s), counter 2 will be cleared by the next input pulse before N counts are completed, so counter 2
never outputs "1" to the output terminal CA.

When the count time N/f(s) is shorter than the pulse period T(s), the output of the inverter becomes "0" by generating "1" at the terminal CA at the end of counting, and as mentioned above, F and F8 are When "0" is added to input terminal B, "1" is generated at the corresponding output terminal D and "0" is generated at the output terminal C, and these are held.

That is, F. FB is reset.

F. The output terminal C of F8 is connected to one input terminal of the NAND gate 9, the output terminal D is connected to one input terminal of the NAND gate 10, and the other input terminal M of each NAND gate is connected to the pulse input terminal 4. It is connected.

Therefore, when there is no input pulse from terminal 4, the outputs of NAND gate 9 and NAND gate 10 are both "1".
”.

When the input pulse arrives, F. Of both output terminals of the FB, the output of the NAND gate connected to the side producing "1" becomes "0", and the output of the NAND gate connected to the side producing "0" becomes "1". becomes.

Therefore, as mentioned above, when the next input pulse arrives while the CA terminal of counter 2 is generating "1", the NAN
produces a "0" at the output of the D gate 10, thereby causing the F.
Fli outputs "1" to the corresponding output terminal H and holds it after the input/output pulse has passed.

F. FB inverts its state again by the next output pulse of the delay circuit 6, and outputs "1" to output terminal C and "0" to output terminal D.
This may be because the input voltage from terminal 4 is "0". Both input terminals of F10 are "1" and the state does not change.

When the count time N/f(s) is longer than the pulse interval T(5), the counter 2 is cleared before the end of counting as described above, so that "1" is not generated at the CA terminal.

Therefore F. Input terminal B of F8 is always "1", and F.
FB produces "1" at output terminal C and "0" at output terminal D when the output pulse of delay circuit 6 becomes "0".

Therefore, due to the arrival of the input pulse from terminal 4, NAND
The output of gate 9 becomes "0", and F. F11 generates "1" at the output terminal G and holds it.

From the above explanation, depending on the length of the count time N/f(s) and the pulse interval T(s), when N/f<T, F
．． "1" is produced at the output terminal H of F11, and when N/f>f, "1" is produced at the output terminal G.

By connecting the output terminal H to the column output terminal 12, it is possible to determine whether the count time N/f(S) is shorter or longer than the pulse interval T(s) depending on whether the output state of the terminal 12 is "1" or "0". can be known.

FIG. 3 is a time chart showing the operation of each part in FIG. 1.

In the figure, a is the input pulse s1 at the pulse input terminal 4, b is the reference pulse S2 from the pulse oscillator 1, c is the output signal S3 of the delay circuit 6, d is the output signal S4 of the programmable counter 2, and e is the F. The output signal S5, f at terminal C of F8 is F. Output signal S6 of terminal D of F8, g is NA
The output signal S7, h of the ND gate 9 is the output signal S7, h of the NAND gate 10.
The output signal S8,i of F. Output signal S of terminal G of F11
9.j is F. They each represent the output signal of the terminal H of F11, that is, the output signal S10 of the external output terminal 12.

Note that the time chart in FIG. 3 (here, the interval T1 between input pulses p1 and p2, and the interval T2 between input pulses p2 and p3 represent the case where T1>N/fT2<N/f, respectively.

Also, if the interval between the input pulse p1 and the pulse one before p1 is T0, then T.

An example is shown assuming that >N/f.

After being cleared by the input pulse p1, the programmable counter 2 starts counting the reference pulse S2 from the pulse oscillator again, and outputs a carry-out PCA after N counts.

F. F8 stores carryout PcA and sends it to terminal D “
Note that the next input pulse p2 passes through the NAND gate 10 and outputs "01" to the input terminal F of F.F11.
Enter.

As a result, F. The output terminal G of F11 becomes "0" and the output terminal H becomes "1" to maintain the previous state.

After the input pulse p2 is delayed by the delay circuit td of the delay circuit 6, the programmable counter 2 is cleared and the F. Reset FB.

The programmable counter 2 starts counting the reference pulses again, but before reaching the N count, the next input pulse p3 starts counting.
Carry-out PCA does not occur because it is reset by .

Therefore, pulse p3 passes through NAND gate 9 and F. F
Since "0" is given to the input terminal E of F.11. F11 is inverted and the output signal at the output terminal H changes from "1" to "0", indicating that a detection operation has been performed.

As is clear from the above description, it is necessary that the output pulse of the delay circuit 6 lags the input pulse of the terminal 4 by a pulse width t1 or more.

When the pulse width is set to t1-t00ns as in the above example, the appropriate delay time of the delay circuit 6 is about 150ns.

As a result, F. NAND the information stored in FB
After being taken out to gate 9 or NAND gate 10, programmable counter 2 and F. You can clear F8.

The set number N of the programmable counter 2 can be arbitrarily set externally by the count control section 3.

Therefore, the constant oscillation frequency N/f (Hz) of pulse oscillator 1
This makes it possible to compare the length of the pulse interval T(5) with respect to an arbitrary count time N/f(s).

In this case, the detection error is determined by the programmable counter Since it is within ±1 count of 2, it is within ±1/f.

Therefore, in order to keep the error within 1% of the pulse period, the oscillation frequency of the pulse oscillator 1 should be selected so as to be 1 (T-) for the shortest period of the input pulse.

Furthermore, if the input pulse interval is longer than this, by increasing the set number N of the programmable counter 2, the input pulse interval can always be verified with an accuracy higher than 1%.

As explained above, according to the pulse interval detection method of the present invention, pulse intervals can be verified with high accuracy with a very simple configuration.

The pulse interval detection method of the present invention is useful in a discrimination circuit of a frequency comparator that compares the magnitude of two similar frequencies, but it can also be used for general frequency measurement and period measurement.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the pulse interval detection method of the present invention, FIG. 2 is an explanatory diagram showing input pulses,
FIG. 3 is an operation time chart of each part in the embodiment of FIG. 1. 1...Pulse oscillator, 2...Programmable counter,
3... Count control section, 4... Pulse input terminal to be measured,
5, 7... Inverter, 6... Delay circuit, 8, 11...
Set reset flip-flop, 9.10...NAN
D gate, 12...External output terminal.

Claims (1)

[Claims] 1. A programmable counter that sets the standard time by counting the reference pulse that is cleared for each pulse to be measured and outputting a carry-out signal when the externally set full count value is reached; a first memory circuit that inverts and holds the state when it is set to a state and receives a carry-out signal of the programmable counter; and a first memory circuit that reads and stores the state of the first memory circuit for each pulse to be measured. 2. A pulse interval detection method, characterized in that the pulse interval detection method is characterized in that the pulse interval detection method is characterized in that the pulse interval detection method is characterized in that the pulse interval detection method is characterized in that the pulse interval detection method is characterized in that the pulse interval detection method is characterized in that the pulse interval to be measured is long or short with respect to an arbitrary standard time.