JPS588767B2 - linear amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a linear amplifier circuit suitable as a linear amplifier of an operational amplifier circuit.

Conventional operational amplifier circuits (operational amplifiers) include bipolar operational amplifiers formed using bipolar transistors,
There are mixed types of bipolar and MOS, but all MO
S-type operational amplifiers are not yet commercially available.

When an all-MOS type operational amplifier is used, the following advantages are provided.

(a) In the case of a bipolar type, the VBE (base-emitter voltage) and hFE (current amplification factor) of the transistor have a small temperature dependence, and the temperature coefficient of the current is positive, so thermal runaway is likely to occur. , MOS transistors have a region where the temperature coefficient of current is zero, and even if the transistor deviates from this region, as long as it operates in the saturation region, the temperature coefficient of current is negative, so thermal runaway will not occur.

(b) In the case of a bipolar type, a somewhat large input bias current is essential, but in the case of a MOS transistor, since it is an insulated gate type and has a very high input impedance, the input bias current is extremely high on the order of PA (picoampere). A small value is sufficient.

(c) Compared to bipolar transistors, MOS transistors are easier to integrate into integrated circuits, and operational amplifiers can be constructed with a smaller chip area.

On the other hand, a drawback of using a MOS transistor is that its Vth (threshold voltage) varies during the manufacturing stage, so that the input offset voltage tends to increase.

Generally, the relationship between the input and output of a differential amplifier circuit (differential amplifier) is expressed by the following equation.

Vo1=K (VH − V(-) }+VB where V.

1 is the output voltage of the differential amplifier, K is the gain of the differential amplifier, V
(+) is the non-inverting input voltage, V(-) is the inverting input voltage, V
B is the output voltage of the differential up when V(+)=V(-), and this voltage VB is determined depending on the power supply voltage.

In other words, in an ideal differential amplifier, V(+)=V(-
), the output voltage V01 should be fixed at a constant value VB.

However, depending on the level of V(+)=V(-), the level of V01 usually differs between, for example, 2 volts and 3 volts.

In other words, when input V(+) is considered constant as a reference voltage,
A differential amplifier can be thought of as a linear amplifier circuit (linear amplifier) for input V(-), but depending on the setting of V(+), V
Since the 01 potential changes, it can be said that the circuit threshold voltage (circuit Vth) of the differential amplifier changes due to V(+).

Here, the differential amplifier circuit Vth is V(+)=V(-
), and it is preferable that this V01 be at the center of the high gain amplification possible region of the input/output efficiency of the next stage linear amplifier.

When the circuit Vth of the differential amplifier changes, assuming that the circuit Vth of the next stage linear amplifier is always constant, V(+
), the DC level of Vo1 does not match the linear amplifier circuit Vth, and V01 is input in a region where minute changes in V01 cannot be detected.
This effectively reduces the voltage gain of the operational amplifier.

Here, the circuit Vth of the next stage linear amplifier means that the input voltage VIN and output voltage Vout of the linear amplifier circuit are V■N.
It can be considered that the voltage VIN or Vout when =Vou1, and the gain becomes large here.

Therefore, in order to widen the dynamic range (operating input voltage range) of an operational amplifier, it is necessary to make the output DC level of the differential amplifier and the circuit vth of the linear amplifier as close as possible.

The present invention has been made in view of the above circumstances, and aims to provide a linear amplifier circuit with a high gain by having a configuration in which the circuit Vth can follow and change the input DC level.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an operational amplifier.

In the figure, 1 indicates inverting input V(-) and non-inverting input V(+)
The linear amplifier 2 amplifies the output of the differential amplifier 1, and the buffer circuit 3 receives the linear amplifier output V.

2 to V. 3 and lead out of the circuit.

The circuit v1h of the linear amplifier 2 The compensation circuit 4 operates as a linear amplifier that receives the input V (-) V (+) of the differential amplifier 1, and uses its output vc as the circuit V of the linear amplifier 2.
th is adjusted, and the operational amplifier is operated with a constant voltage gain regardless of the settings of V(+) and V(-).

FIG. 2 is a specific example of the circuit shown in FIG.

Note that this circuit is an integrated circuit formed on the same semiconductor substrate, and the MOS transistors used are all enhancement type.

That is, in the differential amplifier section 1, the VD level supply terminal 11 and the V
A P-channel type MOS transistor Tr1 that operates in a saturation region and an N-channel type load MOS transistor Tr2 are connected in series between the SS potential supply terminal 12, the gate of the transistor Tr2 is connected to the VDD potential supply terminal 11, and the transistor Tr1 The gate of the device is connected to its own drain end, and a constant voltage is obtained from there.

Further, between the terminals 11 and 12, there are a P-channel type MOS transistor T for a constant current source, a P-channel type input stage transistor T, 4, and an N-channel type load MOS transistor T, 6, T, 8. A P-channel type input stage transistor Tr5 and an N-channel type load M are connected in series and between the drain end of the transistor Tr3 and the terminal 12.
OS transistors T,, Tr, are connected in series.

1. The gate of transistor Tr3 is connected to the drain end of transistor T,1, the gate of transistor Tr4 is connected to the supply end 13 of inverting input V(-), and the gate of transistor T,5 is connected to the supply end of non-inverting input V(+). Connected to end 14.

The drain ends of the transistors Tr4 and Tr5 are phase-connected via a phase compensation coupling capacitor C for lowering the cutoff frequency of the differential amplifier 1, and are connected to a load transistor Tr.
6~Tr9? The gates are commonly connected to the drain ends of the transistors Tr4.

Further, in the circuit Vth compensation circuit 4, between the terminals 11 and 12, a P-channel type transistor TrlO for constant current source,
A parallel circuit of N-channel type MOS transistors Tr11 and Tr1 and N-channel type load MOS transistors T and 13 operating in the saturation region are connected in series.

The gate of transistor Tl-10 is transistor Tr1
The gate of the transistor Tr11 is connected to the non-inverting input supply terminal 14, and the gate of the transistor Tr11 is connected to the drain terminal of the transistor Tr11.
The gate of r12 is connected to the inverting input supply end 13, the substrates of transistors Tr11 and Tr12 are connected to their own source ends, and the gate of transistor Tr13 is connected to the output end of differential amplifier 1.

In this case, the linear amplifier 2 has a two-stage amplification configuration.

In this linear amplifier 2, terminal 11 and output terminal 0. A P-channel MOS transistor T for constant current source is connected between
r14, P-channel MOS transistor Tr1 for amplification
5 are connected in series, and between the terminal 12 and the output terminal 01,
An N-channel type load MOS transistor Tr17 and an N-channel type MOS transistor for amplification are connected in series.

The gate of the transistor Tr14 is connected to the drain end of the transistor Tr1, and the gate of the transistor Tr14 is connected to the drain end of the transistor Tr1.
The gate of transistor Tr17 is connected to the output terminal of differential amplifier 1, and the gate of transistor Tr17 is connected to the output terminal of differential amplifier 1.
It is connected to the source end of 12.

Further, between the terminal 11 and the output terminal Or, a P-channel MOS transistor Tr1 for constant current source and a P-channel MOS transistor Tr19 for 8% amplification are connected in series, and between the terminal 12 and the output terminal 02, an N Channel type load MOS
A transistor Tr21 and an amplifying N-channel type MOS transistor Tr20 are connected in series.

The gate of the transistor Tr18 is the gate of the transistor Tr14.
are commonly connected to the gates of transistors Tr19 and Tr
The gate of transistor Tr20 is connected to the output terminal 01 of the previous stage, and the gate of transistor Tr21 is commonly connected to the gate of transistor Tr17.

Moreover, in the buffer circuit 3, between the terminals 11 and 12,
A P-channel MOS transistor Tr22 and an N-channel MOS transistor Tr23 are connected in series, the gates of these transistors Tr22 and Tr23 are connected to the output terminal 02 of the linear amplifier, and the transistors Tr22 and Tr23 are connected in series.
The drain end of r23 is connected to the operational amplifier output end 15.

In the figure, 16.17 is the offset adjustment terminal, 18
is a stro-bing test terminal.

However, in the differential amplifier 1, in order to maximize the gain in the differential amplification stage, the gm (conductance) of the input stage transistors Tr4 and Tr5 is increased, and the load MOS Tr6 to
The gm of Tr9 is set small.

Furthermore, by applying the drain potential of the transistor Tr6 to the gates of the transistors T, 6 and Tr9, the CM
The aim is to improve RR (common mode component suppression ratio).

That is, when input V(+)=V(-), when the input potential increases, transistors Tr4 and Tr5 approach cutoff,
The drain potential of transistor Tr6 decreases.

Therefore, the transistors Tr6 to Tr9 also approach cutoff, and the drain potential of the transistor Tr7 (output voltage V0
1) tends to be held to a constant value as much as possible.

In the circuit Vth compensation circuit 4, if the input V(+) is considered as a reference voltage, as the potential of the input V(+) (=V(-)) increases, the drain potential of the transistor Tr7 decreases, resulting in a linear Since the input bias voltage V01 of the amplifier 2 is lowered, by lowering the DC level of the output 01 of the linear amplifier 2, the linear amplifier 2 can be operated in the highest gain region.

That is, when the input V(+) (=V(-)) is increased,
The drain potential of the transistor Tr13 increases accordingly, and the on-resistance of the transistor Tr17 becomes low (g
m large), and the circuit Vth of the linear amplifier 21 decreases.

At this time, since the transistors Tr4 and Tr5 approach cut-off, the input bias voltage vo1 is also low, so the linear amplifier 21 amplifies its input with maximum gain.

Since the linear amplifier 22 at the rear stage is also controlled in the same way as the linear amplifier 21 at the front stage, the output of the amplifier 21 is amplified at the maximum gain.

The buffer circuit 3 is used to lower the output impedance, and only needs to have a voltage gain of 1 or more.

Further, the transistor Tr1, which is connected in series with the load MOS transistor Tr2 and operates in the saturation region, has a common drain and gate, and a constant potential is applied to the transistors Tr3 and Tr1.
By applying the voltage to the gates of r1o, Tr14, and Tr18, even if the Vth of the P-channel transistor changes, the current can be kept substantially constant, thereby absorbing variations in the Vth of the P-channel transistor.

FIG. 3 is a modification of FIG. 2.

Here, the difference from FIG. 2 is that the channel types of N-channel type MOS transistors Tr11 and Tr12 are changed to P-channel type MOS transistors Tr11' and Tr12'.

Along with this, the transistor Tr16 of the linear amplifier 2
, Tr17 and transistors Tr20, Tr2,
The arrangement of the linear amplifiers is changed, and each linear amplifier output is taken from the source side of the transistors T, 17, T, and 21.

The operation in this case is almost the same as in FIG.

FIG. 4 is for explaining a modification of the linear amplifier 2 shown in FIG. 2. In FIG.

To adjust the circuit vth of this circuit, the gate input V22 side of the transistor Tr17 may be constant and the gate input V21 side of the transistor Tr14 may be made variable, or the transistor to which a constant gate input is supplied may be omitted. Good too.

Further, the arrangement of transistors Tr14 and Tr15 or the arrangement of transistors Tr16 and Tr17 may be interchanged.

Even in this case, the gain of the linear amplifier 2 can be increased in the same way.

5 and 6 are for explaining a modification of the circuit Vth compensation circuit 4 of the previous embodiment, and FIG. 5 corresponds to the case of FIG. 2, and FIG. 6 corresponds to the case of FIG. 3. .

This circuit can freely change the circuit Vth using either one of the two inputs IN1 and IN2.

That is, here, the circuit Vth means, for example, when input voltage IN2 is considered as the reference voltage in FIG.
Since it can be said that this is the voltage when IN becomes equal to the output voltage out2, the circuit Vth can be changed by the way the input voltage IN2 is set.

Also, the circuit in Figure 5 can be seen as a source follower when viewed from the output out2, and a linear amplifier when viewed from the output out1, and the circuit in Figure 6 can be seen as a source follower when viewed from the output out1.
It can be seen as a source follower when viewed from above, and a linear amplifier when viewed from the output out2.

Therefore, when this circuit is used only as the source follower or linear amplifier, the load transistor Tr
One of Tr10 and Tr13 can be omitted.

As described above, according to the present invention, a linear amplifier circuit with a high gain can be provided because it can operate at the point with the highest amplification degree.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an operational amplifier circuit to which an embodiment of the present invention is applied, FIGS. 2 and 3 are detailed diagrams of the circuit, and FIG.
Figure 5 is a circuit diagram for explaining another embodiment of the present invention.
6 are circuit diagrams showing a partial application example of FIGS. 2 and 3. T, 14, Tr15...Load MOS transistor, T
, 15, Tr16...drive MOS transistor, V
DD, Vss...power supply, IN...input, out...
·output.

Claims (1)

[Claims] 1. A first channel type first MOS transistor is provided between one potential supply end and the output end, and a second channel type first MOS transistor is provided between the other potential supply end and the output end. A second MOS transistor is provided, a common input signal is supplied to the first and second MOS transistors, and the first or second MOS transistor is connected between the one or the other potential supply terminal and the output terminal. The first channel type or the second channel type for the transistor.
A third channel type MOS transistor is inserted in series,
By supplying a voltage containing a DC component that changes according to the DC level of the input signal to the gate of the third MOS transistor, the circuit threshold voltage of the third MOS transistor is changed in a direction that matches the DC level of the input signal. A linear amplification circuit characterized by comprising means. 2. Claim 1 further comprises constant current load means inserted in series with the second or first MOS transistor between the other or one potential supply end and the output end. The linear amplifier circuit described.