JPS5824041B2 - operational amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an operational amplifier circuit composed of MOS type transistors.

Conventional operational amplifier circuits (opamps) include bipolar operational amplifiers formed using bipolar transistors,
There are mixed types of bipolar and MOS, but all MO
S-type operational amplifiers are not yet commercially available.

When an all-MOS type operational amplifier is used, the following advantages are provided.

(a) In the case of bipolar type, transistor VBE (base-emitter voltage) and hFE (current amplification factor)
The temperature dependence of MOS transistors is small, and the temperature coefficient of current is positive, so thermal runaway is likely to occur. However, MOS transistors have a region where the temperature coefficient of current is zero, and even if the transistor deviates from that region, As long as the device operates in the saturation region, thermal runaway will not occur because the temperature coefficient of current is negative.

(b) In the case of bipolar type, a reasonably large input bias current is required, but in the case of MO8 + - run lister,
Since it is an insulated gate type and has a very high input impedance,
The manual bias current can be a very small value on the order of PA (picoamperes).

(/υ Compared to bipolar type transistors, MOS transistors are easier to integrate into integrated circuits, and operational amplifiers can be constructed with a small chip area.

On the other hand, a drawback of using a MOS transistor is that the input offset voltage tends to increase because its Vth <threshold voltage) varies during the manufacturing stage.

Generally, the relationship between the input and output of a differential amplifier circuit (differential amplifier) is expressed by the following equation.

VOI = K (V(-)3-V(-3) +VB where V.

1 is the output voltage of the differential amplifier, K is the gain of the differential amplifier, V
(+) is the non-inverting input voltage, VH is the inverting input voltage, and vB is the output voltage of the differential amplifier at V±)-VC-'), and this voltage vB is determined depending on the power supply voltage.

That is, in an ideal differential amplifier, when ■(±-■(→), the output voltage V.

1 should be fixed at a constant value VB.

However, depending on the level of V(a)-V(→, the Vo10 level usually differs between, for example, 2 volts and 3 volts.

In other words, when input V (e) is considered constant as a reference voltage,
A differential amplifier can be thought of as a linear amplifier circuit (linear amplifier) for input VH, but depending on the setting of V (+).

Since one potential changes, it can be said that the circuit threshold voltage (circuit Vth) of the differential amplifier changes depending on V (e).

Here, the differential amplifier circuit Vth is V(+)=V
(This ■ can be thought of as the output voltage Vo1 when →.

1 is preferably located in the center of the high gain amplification possible region of the human output characteristic of the next stage linear amplifier.

When the differential amplifier circuit Vth becomes i, assuming that the next stage linear amplifier circuit Vth is always constant, V
(V depends on the setting of +3.

] in the region where the DC level does not match the linear amplifier circuit Vth and minute changes in vol cannot be detected.

Since 1 is input, the voltage gain of the operational amplifier is effectively reduced.

Here, the circuit Vth of the next stage linear amplifier is the input terminal VIN and output voltage V of the linear amplifier circuit.

ut is vIN-■. The voltage VIN or V when ut.

It can be considered as ut, and the gain is large here.

Therefore, in order to widen the dynamic range (operating input voltage range) of the operational amplifier, it is necessary to make the output DC level of the differential amplifier as close as possible to the circuit Vth of the linear amplifier.

The present invention was made in view of the above circumstances, and the circuit Vth of the next stage linear amplifier is
The present invention aims to provide an operational amplifier circuit that can improve the above-mentioned conventional problems by adopting a configuration in which the following effects occur.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an operational amplifier.

In the figure, 1 is a differential amplifier whose inputs are an inverting input V (→ and a non-inverting input V(+)), a linear amplifier 2 amplifies the output of the differential amplifier 1, and a buffer circuit 3 amplifies the linear amplifier output V.

2 to V. 3 and lead out of the circuit.

The circuit Vth compensation circuit 4 of the linear amplifier 2 operates as a linear amplifier that receives the inputs VH and V (A) of the differential amplifier 1, and outputs Vth.

Adjust the circuit Vth of linear amplifier 2 with (1)
.

■(The operational amplifier operates with a constant voltage gain regardless of the setting of →.

FIG. 2 is a specific example of the circuit shown in FIG.

Note that this circuit is an integrated circuit formed on the same semiconductor substrate, and all MOS transistors used are amplifier type.

That is, in the differential angle section 1, the VDD potential supply end 1-1
A P-channel MOS transistor Tr1 that operates in the saturation region and an N-channel load MOS transistor Tr2 are connected in series between the transistor Tr2 and the VSS potential supply terminal 12, and the gate of the transistor Tr2 is connected to the VDD potential supply terminal 11. The gate of Tr is connected to its own drain end and a constant voltage is obtained from there.

Further, between the terminals 11 and 12, a P-channel type MOS transistor Tr3 for a constant current source, a P-channel type input stage transistor Tr4, an N-channel type load MOS transistor Tr6. Tr8 are connected in series, and between the drain end of the transistor Tr3 and the terminal 12, there is a P
Channel type human power stage transistor Tr5, N channel type load MOS transistor Tr7. Trg are connected in series.

The gate of transistor Tr3 is transistor Tr,
The gate of the transistor Tr4 is connected to the supply terminal 13 of the inverting input V(()), and the gate of the transistor Tr5 is connected to the supply terminal 1 of the non-inverting input V(+).
Connected to 4.

The drain ends of the transistors Tr4 and Tr are connected to each other through a phase compensation coupling capacitor C for lowering the cutoff frequency of the differential amplifier 1, and the gates of the load transistors Tr6 to Trg are connected to the drain ends of the transistor Tr4. Commonly connected.

Further, in the circuit Vth compensation circuit 4, between the terminals 11 and 12, P-channel transistors Tr, o,
N-channel type MO8) Run lister Tr1. and Tr,
20 low-voltage circuit, N-channel type load M operating in saturation region
OS transistors Tr13 are connected in series.

The gate of the transistor TrlO is the transistor Tr,
The gate of the transistor Trl+ is connected to the non-inverting input supply terminal 14, the gate of the transistor Tr12 is connected to the inverting input supply terminal 13, and the transistor Tr1+ is connected to the drain terminal of the transistor Tr12.
'-) is connected to the source terminal of the transistor Tr13, and the gate of the transistor Tr13 is connected to the output terminal of the differential amplifier 1.

In this case, the linear amplifier 2 has a two-stage amplification configuration.

In this linear amplifier 2, terminal 11 and output terminal 01
A P-channel MOS transistor Tr14 for constant current source, a P-channel MOS transistor Tr14 for amplification, and a run lister T
r15 are connected in series, and between the terminal 12 and the output terminal 0□, an N-channel type load MOS transistor Tr1□,
N-channel type MOS transistors for amplification are connected in series.

The gate of the transistor TrH is the transistor Tr,
The transistor Tr15 is connected to the drain end of the transistor Tr15.

The gate of Tr16 is connected to the output terminal of differential amplifier 1,
The gate of transistor Tr1□ is connected to transistor Tr1.
, is connected to the north end of 'l'r1°.

Moreover, between the terminal 11 and the output terminal 02, there is a P-channel type MO8I-transistor TrB3 for a constant current source, and a P channel type transistor for amplification.
A channel type MOS transistor Tr1g is connected in series, and an N-channel type load MO8) run lister Tr2□ and an amplifying N-channel type MO8) run lister Tr2o are connected in series between the terminal 12 and the output terminal 02.

The gate of the transistor Tr18 is a Trumpet collar Tr,4
are commonly connected to the gates of transistors Tr1. j T
The gate of r20 is connected to the output terminal o1 of the preceding stage, and the gate of transistor Tr2□ is commonly connected to the gates of transistors Tr and □.

Moreover, in the buffer circuit 3, between the terminals 11 and 12,
A P-channel MoS transistor Tr22 and an N-channel MOS run transistor Tr23 are connected in series, and the gates of these transistors Tr22 and Tr23 are connected to the output terminal o2 of the linear amplifier, and the transistor Tr23 is connected to the output terminal o2 of the linear amplifier.
The drain end of 2□j Tr23 is connected to the operational amplifier output end 15.

In the figure, 16 and 17 are offset adjustment terminals, and 18
In the differential amplifier 1, in order to maximize the gain in the differential amplification stage, the input stage transistors Tr4. Increase gm (conductance) of Tr5, load MO8Tr6~
The gm of Trg is set small.

Also, by applying the drain potential of transistor Tr60 to the gates of transistors Tr6 to Trg, CI
The aim is to improve VIRR (common-mode component suppression ratio).

That is, when the input voltage is V(1)-V(c), when the input potential increases, the transistors Tr4 and Tr5 approach cutoff, and the drain potential of the transistor Tr6 decreases.

Therefore, the transistors Tr6 to Trg also approach cutoff, and the drain potential (output voltage V) of the transistor Tr7.

1) tends to be held to a constant value as much as possible.

In the circuit Vth compensation circuit 4, if the input V(+) is considered as a reference voltage, as the potential of the human input V(e)(-V(→) increases, the drain potential of the transistor Tr7 decreases, and the linear amplifier 20 input bias voltage V.

1 becomes low, by lowering the DC level of the output 01 of the linear amplifier 2, the linear amplifier 2 can be operated in the highest gain region.

That is, when the input V(g) (=V(f)) is increased, the drain potential of the transistor Tr13 becomes higher by that amount, and therefore the on-resistance of the transistor Tr170 becomes lower (gm
(large), and the circuit Vth of the linear amplifier 21 decreases.

At this time, transistor Tr4. As Tr5 approaches cutoff, the input bias voltage V.

1 is also low, so linear amplifier 2 amplifies its input with maximum gain.

The linear amplifier 22 at the rear stage is also the linear amplifier 2 at the front stage,
Since it is controlled in the same way as , the output of amplifier 2□ is amplified with maximum gain.

The buffer circuit 3 is used to lower the output impedance, and only needs to have a voltage gain of 1 or more.

It is also connected in series with the load MOS transistor Tr2,
The transistor Tr, which operates in the saturation region, has its drain and gate in common and a constant potential is applied to the transistor Tr.
By applying the current to the gate of 35 Trio 2 Tr14 j Tr18 , even if the Vth of the P-channel transistor changes, the current can be kept substantially constant, thereby absorbing variations in the Vth of the P-channel transistor.

FIG. 3 is a modification of FIG. 2.

Here, the difference from FIG. 2 is that the N-channel MOS transistor Tr11. The difference is that the channel type of Tr1□ is changed to P-channel type MOS transistors Tr'1□ and Tr'1□.

Along with this, the transistor Tr16 of the linear amplifier 2
, Tr1□ and transistor Tr2 (17
Tr2. The arrangement of the linear amplifiers is changed, and each linear amplifier output is taken from the source side of the transistors Tr1□+Tr21.

The operation in this case is almost the same as in FIG.

FIG. 4 is for explaining a modification of the linear amplifier 2 shown in FIG. 2. In FIG.

Here, in order to adjust the circuit Vth of this circuit, the gate input Vg□ side of the transistor Tr1□ may be constant, and the gate input power V8 side of the transistor 'I''r14 may be made variable, or a constant gate power is supplied. The transistor may be omitted.

Further, the arrangement of transistors Tr+4 and Tr15 may be exchanged, or the arrangement of transistors Tr16 and Tr1□ may be exchanged.

Even in this case, the gain of the linear amplifier 2 can be increased in the same way.

5 and 6 show the circuit Vth compensation circuit 4 of the previous embodiment.
5 corresponds to the case of FIG. 2, and FIG. 6 corresponds to the case of FIG. 3.

This circuit is a two-person IN1. The circuit Vth can be freely changed using either one of IN2.

That is, here, the circuit Vth means, for example, when input voltage IN2 is considered as the reference voltage in FIG.
It can be said that this is the voltage when N1 is equal to the output voltage 0UT2, so depending on how the input voltage IN2 is set, the circuit Vth
can be changed.

Also, the circuit in Figure 5 can be seen as a source follower when viewed from the output 0UT2, and a linear amplifier when viewed from the output 0UTI.
When viewed from 'l, it can be seen as a source follower, and when viewed from output 0UT2, it can be seen as a linear amplifier.

Therefore, when this circuit is used only as the source follower or linear amplifier, the load transistor Tr
One of Tr1o and Tr13 can be omitted.

As explained above, according to the present invention, since the circuit Vth of the linear amplifier is made to follow the output DC level of the differential amplifier according to each input terminal of the differential amplifier, calculations that can widen the dynamic range of the input voltage This can be provided by an amplifier circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
Figure 3 is a specific circuit diagram of the same configuration, Figures 4 to 6 are
The figure is a circuit diagram showing an application example of the present invention. 1...Differential amplifier, 2...Linear amplifier, 3...Circuit Vth compensation circuit.

Claims (1)

[Claims] 1 A differential amplifier circuit between the first power supply and the second power supply,
The differential amplifier circuit is configured by connecting a threshold compensation circuit and a linear amplifier circuit in parallel, and the differential amplifier circuit includes a first MOS run lister that receives a first input signal, a second MOS that receives a second input signal, and a second MOS that receives a second input signal.
MOS) run lister, a current source connected between the first power supply of each of these MOS transistors, and a current source connected between the first power supply of each of these MOS transistors;
The threshold compensation circuit includes a load circuit connected between the drain of the S transistor and a second power supply, and the threshold compensation circuit includes a third MOS (Run Lister) that receives the first input signal, and a fourth MOS (MOS) that receives the second input signal. MOS) run lister, these third and fourth
A current source connected between the drain of the MOS) run lister and the second power supply, and a current source connected between the source of the run lister and the second power supply of the third and fourth MOS The linear amplifier circuit has a fifth MOS transistor that receives the output signal of the second MOS transistor, and the linear amplifier circuit receives the output signal of the second MOS transistor.
8) the current source connected between the source of the run lister and the first power supply; the second drive MO8) the fifth MOS connected between the source of the run lister and the second power supply;
A sixth MOS that receives the drain signal of the transistor as input.
An operational amplifier circuit comprising a transistor and an output point where the drains of the first and second driving MOS transistors are connected to each other.