JPS5887639A - Information processor - Google Patents

Abstract

PURPOSE:To easily grasp the change in a lot of data, by providing an instruction logging out the status and hardware information to a processor, and transferring the hardware status information of the instruction level. CONSTITUTION:A processor status transfer instruction transmitted from a processor 1 to a transfer control section 302 consists of a transfer instruction section 201 indicating the transfer of the status information to an external storage device 303, the 1st address section 202 designating which regional information is taken as transferred information, and the 2nd address section 203 designating the area for the storage to the storage device 303 instructed at the instruction section 201. When a processor status transfer instruction is issued, the instruction transferring the status signal of the hardware via a path (a) is transmitted to a control section 302, which stops the processing of the device 1 at the path (b), fetches the hardware status information via a path (c) from the device 1, designates the storage area of the storage device 303 via a path (d), allowing to easily grasp a lot of data change.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device having a work memory that temporarily stores state information such as hardware registers that cannot be referenced or state transition information for program processing by program level instructions. The present invention relates to an information processing device that can trace these changes over time to obtain analysis information when a failure occurs.

In general, information processing equipment has a small-scale memory device dedicated to tracing as hardware, and by writing hardware status information such as data set condition signals of registers to this memory device at regular intervals, it is possible to perform On the other hand, in software, the contents of program-accessible areas such as control registers, programs, and data registers and software information are dumped at the request of the program, which is necessary for failure analysis. Obtaining software information.

FIG. 1 is a diagram for explaining the trace function in the prior art. In FIG. 1, l indicates a processing device, which performs program processing. The trace control unit 2 sends signals to the trace memory 3 to instruct the start and stop of tracing, or sends codes from the trace memory 3 to the processing device l. The trace memory 3 is a storage mechanism that writes signals from the processing device 1 at regular intervals and updates the trace memory address to the next address. The display panel 4 is a control unit that displays or prints the contents of the trace memo 173.

When the processing device 1 starts program processing, a signal indicating that program processing is being executed is sent to the trace control section 2 via the path a. In the trace control section 2,
Upon receiving this signal, a trace start activation signal is sent to the trace memory 3 via a route. The trace memory 3 writes the control signal or data signal group received from the processing device I via the path C for tracing to the trace memory 3 at regular intervals while updating the address in response to the trace start activation signal.

When the processing device 1 stops due to a failure that makes it impossible to continue program processing, the signal indicating that the program processing is being executed, which was sent to the tracer control unit 2 via path a, is turned off. When the trace control unit 2 learns that the program processing has stopped +L because the H signal is turned off, it sends a tracer stop activation signal to the route. The tracer memory 3 that has received the instruction to stop the tracer through the route stops writing to the trace memory 3) and prohibits updating of the trace memory address. Then, the trace control unit 2 sends the program processing stop signal of the processing device l sent via the path a to the display panel 4 via the path eK.

On the display panel 4, the status information of the processing device l or the processing device l stored in the trace memory 3 is displayed via the path f.
Obtain control signal trace information.

The display panel 4 is instructed to read the fault information by issuing the instruction to the display panel 4 manually or by using a diagnostic program of the processing device.

In this way, the conventional hardware fault #l@ tracing function always checks the execution status of the processing unit and writes data, and if the trace memory capacity is exceeded, address love-aland processing is performed to remove old trace data. Since the latest trace data is written to the area, it is possible to trace only up to the memory capacity cycle of the trace memory before the processing device is stopped due to a failure. This means that the capacity of the trace memory is limited, so for the program execution processing step of the processing unit, the trace ρ■ is only limited to an extremely short period until the failure stops, and the trace memory, such as data in a register, is It has the disadvantage of not being able to trace large amounts of data changes.

Further, in the conventional method, it was necessary to prepare a signal group dedicated to the tracer in the processing device, and furthermore, it was necessary to prepare a dedicated trace memory. Also, even when tracing fault information, the data width of the tracer memorino is increased,
Attempting to trace write data in addition to control signals would require a large amount of memory, making it difficult to put it into practical use.

That is, in the conventional no-ware tracer method, f1! is relatively long. (For example, channel data transfer processing)
It was not possible to provide information for analyzing one type of failure, or analysis information for failures such as failure of the data itself (#1).

On the other hand, in dump program processing by software, data in the program reference area can be saved as described above, but leadware information (in other words, channel registers) cannot be referenced at all. In addition, the timing for stamping each block reference area is after a failure occurs, and the progress of program processing during the process can be traced by manually simulating the program part of the stamp area. This is the method of failure analysis.It is true that it takes a lot of man-hours, but it is based on the assumption that "this is how Zosta should be" and traces it. Failure analysis was difficult.

In general, problems with processing equipment are caused by hardware failures or software program failures. There are many cases where this is not achieved, and the customer's trust is often lost as well as the system's reliability.

In the conventional technology, the distinction between hardware failure and software failure does not provide failure data for analysis.

The present invention eliminates the problems of the prior art mentioned above and provides an information processing device that outputs data in hardware to an external storage device by giving a command to log out status information and hardware information of the processing device. There is a particular thing.

Hereinafter, the present invention will be described in detail with reference to one embodiment shown in the drawings.

FIG. 2 shows the format of the processing device state transfer command used in the present invention. That is, the processing device state transfer instruction is a transfer instruction unit 2011 of the processing device that instructs the processing device to transfer the state information of the hardware inside the processing device, including hardware registers and memory that cannot be referenced by general instructions, to an external storage device. A first address section 202 that specifies which area information of the hardware status information is to be transferred to the external storage device, and a storage area when storing the transfer information to the external storage device specified by the transfer instruction section 201. It consists of a second address section 203 that specifies.

FIG. 3 is a hardware configuration diagram, where l indicates a processing device,
Performs program processing. The transfer control unit 302 uses the processed value fi
Signal processing to start and stop the ll is sent to the ll. It also stores hardware status information. The external storage device 303Fi stores transfer information sent by the transfer control unit 302.

In the processing device l, when the processing device state transfer command in the program shown in FIG. A signal specifying this is sent to the transfer control unit 302.

The transfer control unit 302 immediately executes the processing of the processing value (l!ll) by route according to the above instructions and specifications, takes in the hardware state information of the corresponding processing device l via route C according to the transfer information specification, and transfers the process to route C. d, the transfer information is stored in the designated storage area of the external storage device 303.

After storing the transfer information, the transfer control unit 302 activates the processing value a1 through the route, so that the processing device continues processing.

FIG. 4 shows the flow of command processing in processing device I when a processing device status transfer command is issued, and the flow of processing in transfer control unit 302, which performs a logout operation in response to an instruction from the processing device. So, (a) is the processing value [processing of 1, (1)
) indicates the processing of the transfer control unit 302.

That is, when a state transfer command is issued by the processing device 1, the transfer control unit 302 is activated and the processing of the transfer control unit 302 is started. Hereinafter, the related operations of the processing value [1 and the transfer control unit 302 are to capture a storage area by specifying a storage area, and to capture transfer information by specifying transfer information. Next, the processing value fil waits for a completion report from the transfer control unit 302, and during that time the transfer control unit 302 processes the process PI! The processing of the transfer control unit 302 is ended by instructing to stop the device l, logging out the processing device information, instructing the start of the processing device l, and reporting the completion.

On the other hand, the processing device 1111 receives the completion report from the transfer control unit 302 and ends the processing of the processing device.

Note that the above-described processing device state transfer command processing can also be executed under hardware control when updating the elapsed time period and issuing interrupt processing such as input/output interrupt operations.

As is clear from the explanation below, the following effects can be obtained according to the present invention.

By making it possible to transfer hardware status information at the fi+ command level, it is possible to log out with the hardware test results reflected.

(2) By transferring hardware status information at the hardware level, changes in large amounts of data can be easily understood.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the trace function of a conventional information processing device, FIG. 2 is a diagram showing the format of a processing device state transfer command used in the present invention, and FIG. 3 is a diagram showing an embodiment of the present invention. −
, FIG. 4 is a flowchart for explaining the operation of FIG. 3. 1... Processing device, 302... Transfer control unit, 303.
...External storage device. Figure 1 AJ] 202 Otori Figure 3 Figure 4 IQ)

Claims (1)

[Claims] l In an information processing device that performs operational processing using a program, a specific supporting instruction is issued to transfer hardware state information inside the processing device, including hardware registers, memory, etc. that cannot be referenced by general instructions, to an external storage device. , an information processing apparatus characterized in that, in accordance with the instruction of the specific command, information in a specified area of the hardware status information is transferred to an external storage device and stored in the specified storage area.