JPS5885546A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5885546A
JPS5885546A JP18325381A JP18325381A JPS5885546A JP S5885546 A JPS5885546 A JP S5885546A JP 18325381 A JP18325381 A JP 18325381A JP 18325381 A JP18325381 A JP 18325381A JP S5885546 A JPS5885546 A JP S5885546A
Authority
JP
Japan
Prior art keywords
film
mask
forming
oxide film
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18325381A
Other languages
Japanese (ja)
Inventor
Yasuo Matsumoto
松元 保男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP18325381A priority Critical patent/JPS5885546A/en
Publication of JPS5885546A publication Critical patent/JPS5885546A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To suppress a narrow channel effect phenomenon by forming a sectional sector-shaped film which narrows downwardly on an oxidation resistant film formed above a region for forming an element of a semiconductor substrate, implanting impurity ions with the sector-shaped film as a mask and forming a field oxidized film with the resistant film as a mask. CONSTITUTION:The entire surface of a silicon oxidized film 25 is etched to the surface of a photoresist film 24 with ammonium solution, thereby exposing the surface of the film 24. Subsequently, the film 24 is etched and removed, thereby forming a sectional sector-shaped silicon oxidized film 25 which narrows downwardly. Then, with the film 25 as a mask a silicon nitrided film 23 is etched and removed by a chemical dry etching method. Thereafter, with the film 25 as a mask channel stopper impurity (such as boron) ions are implanted to the surface of a substrate 21, thereby forming a p<+> type field inversion preventive region 26.

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に係り、特にMOS−L
SIの素子分離技術の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
This article relates to improvements in SI element isolation technology.

従来、たとえばMOS−LSIの素子分離技術として、
いわゆる選択酸化法が一般に用いられていた。以下、第
1図を参照してその選択酸化法の工程を簡単に説明する
。半導体基板(たとえばP型、結晶方位[100])7
の表面に酸化膜2を形成シ2、この酸化膜2上に耐酸化
性マスクたとえばシリコン窒化膜3を堆積1.、/4’
ターニングする。その後、フィールド部に不純物たとえ
ば?ロンをイオン注入、添加して反転防止領域4を形成
する。次に、フィールド酸化を行ってフィールド酸化膜
5を形成し7選択酸化を行うものである。
Conventionally, for example, as an element isolation technology for MOS-LSI,
A so-called selective oxidation method was commonly used. Hereinafter, the steps of the selective oxidation method will be briefly explained with reference to FIG. Semiconductor substrate (for example, P type, crystal orientation [100]) 7
An oxide film 2 is formed on the surface of the oxide film 2, and an oxidation-resistant mask such as a silicon nitride film 3 is deposited on the oxide film 2. , /4'
Turn. Then, for example, impurities in the field part? The inversion prevention region 4 is formed by ion implantation and addition of ions. Next, field oxidation is performed to form a field oxide film 5, and 7 selective oxidation is performed.

しかI−ながら、上述した選択酸化法による高集積化製
造工程においては次のような欠点がある。すなわち、フ
ィールド酸化膜5の幅が単に写真食刻法の技術限界で決
定されるだけでなく、それ以外にいわゆるバーズビーク
の長さが加わり、フィールドの寸法のg細ヒに限界があ
る。さらに、チャネルストッパ用にイオン注入した?ロ
ンがフィールド酸化工程中に横方向にも拡散劃−1素子
形成領域(第1図のA部)かP領域となることにより、
実効的な素子領域が狭くなってしまう。このだめ、トラ
ンジスタ電流が減少したり、しきい値電圧が上ってしま
うなどのナロウチャネル効果を生じる欠点があった。
However, the highly integrated manufacturing process using the selective oxidation method described above has the following drawbacks. That is, the width of the field oxide film 5 is determined not only by the technical limit of photolithography, but also by the length of the so-called bird's beak, which limits the width of the field. Furthermore, did you implant ions for the channel stopper? During the field oxidation process, Ron is also diffused laterally into the 1-element formation region (section A in Figure 1) or the P region.
The effective device area becomes narrower. Unfortunately, this has the disadvantage of causing narrow channel effects such as a decrease in transistor current and an increase in threshold voltage.

本発明は上記事情に鑑みてなされたもので、その目的と
するところは、半導体基板の素子形成のだめの領域上方
に耐酸化性膜を設け、この耐酸化性膜上に下方に狭くな
る断面扇状膜を設け、この扇状膜をマスクとして不純物
をイオン注入し7、上記耐酸化膜をマスクとしてフィー
ルド酸化膜を形成することによって、特にチャネルスト
、パ用にイオン注入した不純物の素子領域への拡散を実
質的に減少させ、高集積度デバイス作成時の障害となる
ナロウチャネル効実現象を抑制し得る半導体装置の製造
方法を提供することにある。
The present invention has been made in view of the above circumstances, and its object is to provide an oxidation-resistant film above a region of a semiconductor substrate where elements are not to be formed, and to form a fan-shaped cross section that narrows downward on the oxidation-resistant film. A film is provided, and impurities are ion-implanted using this fan-shaped film as a mask 7. By forming a field oxide film using the oxidation-resistant film as a mask, the impurities ion-implanted especially for channel strike and passivation are diffused into the element region. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can substantially reduce the narrow channel effect phenomenon that becomes an obstacle when producing highly integrated devices.

以下、本発明の一実施例について図面を参照して曲、明
する。
An embodiment of the present invention will be explained below with reference to the drawings.

1ず、第2図(〜に示すように、半導体基板(たとえば
P型、結晶方位〔100〕)21上に熱酸化法々どによ
り酸化膜22を形成し、この酸化膜22上に耐酸化性膜
上料とし、てたとえばシリコン窒化膜23を堆積する。
1. First, as shown in FIG. For example, a silicon nitride film 23 is deposited as a permanent film material.

次いで、このシリコン窒化膜23上にフォトレジスト1
11224(例えば東京応化社製ポジ型しジス) 0F
PR800)を形成し、このレジスト膜24を通常の写
真罪光法によりパターンニングする。この・ゼターンニ
ング工程後、フォトレジストツヤターンの周端部が、深
さ方向に狭く々るような緩か寿傾斜を待つように180
℃位のベーキングを行う。露出したシリコン窒化膜23
およびフォトレジスト膜24上にシリコン酸化膜25を
形成する。この工程は、表面に、シリコン酸化物粉末を
分散させたシリコン酸化膜形成用塗布液〔だとえばOC
D (東京応化社製・商品名〕〕をスピンナにより塗布
形成し、必要な焼成を施し、て上記シリコン酸化膜25
を形成するものである。
Next, a photoresist 1 is applied on this silicon nitride film 23.
11224 (e.g., positive type resistor made by Tokyo Ohkasha) 0F
PR800) is formed, and this resist film 24 is patterned by a normal photographic method. After this Ze-turning process, the peripheral edge of the photoresist glossy turn has a gentle slope of 180 mm that narrows in the depth direction.
Perform baking at about ℃. Exposed silicon nitride film 23
A silicon oxide film 25 is then formed on the photoresist film 24. In this process, a coating solution for forming a silicon oxide film [for example, OC
D (manufactured by Tokyo Ohka Co., Ltd., trade name)] is applied and formed using a spinner, and the necessary baking is performed to form the silicon oxide film 25.
It forms the

次に、第2図(B)に示すように、シリコン酸化膜25
の表面を弗化アンモニウム溶液などでフォトレジスト膜
24の表面まで全面エツチングを行い、フォトレジスト
膜240表面を露出する。その後、このフォトレジスト
膜24をエツチング除去することにより、下方が狭くな
る断面扇状のシリコン酸化膜25を形成する。次に、第
2図(0に示すように、上記シリコン酸化膜25をマス
クとして、ケミカルドライエ、チング法によりシリコン
窒化膜23をエツチング除去する。次いで、上記扇状シ
リコン酸化膜25をマスクとして、チャネルストツ・や
用の不純物(たとえばボロン)を21内表面にイオン注
入することにより、P型のフィールド反転防止領域26
を形成する。この際、イオン注入時のマスクとなるシリ
コン酸化膜25の形状が断面扇状つ才り逆テーパ状とな
っているため、イオン注入により形成されたP+型のフ
ィールド反転防止領域26の端は、上記逆チー・!形状
のシリコン酸化膜25の上辺長で決定する。次に、第2
図(D)に示すように、耐酸化性のシリコン窒化膜23
上のシリコン酸化膜25および基板2ノ上5− のシリコン酸化膜22を除去し、これにより露出!1.
だシリコン窒化膜23を酸化マスクとして、露出した基
板210表面に燃焼によりフィールドr役化膜27を形
成才る。このように、フィールド酸化膜27を形成する
ためのマスク上にチャネルスト、・ソ領域形成のプiめ
の不純物を断面扇状マスクを介してイオン注入するので
、マスクの端部が異なり、このだめフィールド反転防止
領域26が素子領域まで拡散することがなく、ナロウチ
ャンネル効果が抑制され、トランジスタのしきい値電圧
の抑制が容易となる。
Next, as shown in FIG. 2(B), the silicon oxide film 25
The entire surface of the photoresist film 240 is etched using an ammonium fluoride solution or the like to expose the surface of the photoresist film 240. Thereafter, this photoresist film 24 is removed by etching to form a silicon oxide film 25 having a fan-shaped cross section that is narrower at the bottom. Next, as shown in FIG. 2 (0), using the silicon oxide film 25 as a mask, the silicon nitride film 23 is removed by chemical drying and etching. Next, using the fan-shaped silicon oxide film 25 as a mask, A P-type field inversion prevention region 26 is formed by ion-implanting an impurity (for example, boron) into the inner surface of the channel 21.
form. At this time, since the shape of the silicon oxide film 25, which serves as a mask during ion implantation, has a fan-like, reversely tapered cross section, the edge of the P+ type field reversal prevention region 26 formed by ion implantation is Reverse chi! The shape is determined by the length of the upper side of the silicon oxide film 25. Next, the second
As shown in Figure (D), an oxidation-resistant silicon nitride film 23
The upper silicon oxide film 25 and the silicon oxide film 22 on the upper part of the substrate 2 are removed and exposed! 1.
Using the silicon nitride film 23 as an oxidation mask, a field oxide film 27 is formed by combustion on the exposed surface of the substrate 210. In this way, since the first impurity for forming the channel strike and oxide regions is ion-implanted on the mask for forming the field oxide film 27 through the fan-shaped cross-sectional mask, the ends of the mask are different; The field inversion prevention region 26 does not diffuse into the element region, suppressing the narrow channel effect and making it easier to suppress the threshold voltage of the transistor.

なお、これ以後は通常の製造工程に従いトランジスタを
製造すれば良い。この工程は当業者において慣用技術で
あるからその説明は省略する。
Note that from this point on, the transistor may be manufactured according to a normal manufacturing process. Since this step is a common technique for those skilled in the art, its explanation will be omitted.

次に、llI4酸化性マスク上に形成される断面扇状の
イオン注入用マスク形成の仲の実施例を説明する。捷ず
、第3図(A)に示すように、半導体基板(たとえばP
壁、結晶方位[100〕)31上に1・貧化Hm32を
形成し2、この酸化膜32−ヒに−6一 耐酸化性膜材料としてたとえばシリコン窒化膜33を堆
積する。次いで、このシリコン窪化膜33上にCVD法
により酸化膜34を形成する。
Next, an example of forming an ion implantation mask having a fan-shaped cross section formed on an llI4 oxidation mask will be described. As shown in FIG. 3(A), the semiconductor substrate (for example, P
A 1-depleted Hm 32 is formed on the wall and the crystal orientation [100]) 31, and a silicon nitride film 33, for example, is deposited on this oxide film 32-1 as a -6-oxidation-resistant film material. Next, an oxide film 34 is formed on this silicon dimpled film 33 by the CVD method.

次いで、CF4ガスプラズ体中にさらし7た後、フォト
レジスト膜(図示せず)を酸化膜34上1て 5苓布形成し、このフォトレジスト膜を写真露光法によ
りノーターンニングする。その後、フォトレジストパタ
ーンをマスクとしてNH4F溶液で酸化膜34をエツチ
ングすると、フォトレジストパターンと酸化膜34との
密着側が上記プラズマ照射により劣化し、酸化膜34の
パターンは第3図(B)に示すように深さ方向に狭くな
るようチー・母エツチングされる。このようなテーパニ
ップのエツチングは、上記プラズマ照射法のほか、プラ
ズマ照射を行わなくても、NH4F溶液中にアルコール
などを少量混在させたエツチング溶液を用いてエツチン
グを施り、ても形成できる。このようにして形成したチ
ー、f工、チングにより露出したシリコン窒化膜33お
よび酸化膜34−ヒにフォトレジスト35をスピンナで
塗布L1とのフォトレジスト35の表面を酸素プラズマ
エツチング12、酸化膜34の表面が露出するまでエツ
チングする。そして、この露出[。
Next, after exposure to a CF4 gas plasma 7, a photoresist film (not shown) is formed on the oxide film 34, and this photoresist film is subjected to non-turning by photolithography. After that, when the oxide film 34 is etched with an NH4F solution using the photoresist pattern as a mask, the side where the photoresist pattern and the oxide film 34 are in close contact deteriorates due to the plasma irradiation, and the pattern of the oxide film 34 is as shown in FIG. 3(B). The base is etched so that it becomes narrower in the depth direction. In addition to the plasma irradiation method described above, such a taper nip can be etched by etching using an etching solution containing a small amount of alcohol or the like mixed in an NH4F solution without plasma irradiation. A photoresist 35 is applied using a spinner to the silicon nitride film 33 and oxide film 34 exposed by the thus formed silicon nitride film 33 and oxide film 34 formed by etching. Etch until the surface is exposed. And this exposure [.

た醇化膜34をエツチングすると、第3図(C) K示
すような断面粘状のフォトレジスト35が形成される。
When the fused film 34 is etched, a photoresist 35 having a viscous cross-section as shown in FIG. 3(C)K is formed.

これ以後の工程は、前記実施例における第2図(C) 
、 (D)の工程と同様に実施すればよい。
The subsequent steps are shown in FIG. 2(C) in the above example.
, may be carried out in the same manner as the step (D).

以上説明したように本発明によれば、半導体基板の素子
形成のための領域上方制酸化性膜を設け、この1制酸化
性膜上に下方に狭くなる断面扇状膜を設け、この崩状膜
をマスクとして不純物をイオン注入し、上記耐酸化性膜
をマスクとしてフィールド酸化膜を形成することによっ
て、特にチャネルストッ・2用にイオン注入した不純物
の素子領域への拡散を実質的に減少させ、高集積度デバ
イス作成時の障害となるナロウチャネル効実現象を抑制
し、得る半導体装置の製造方法を提供できる。
As explained above, according to the present invention, an antioxidizing film is provided above a region for forming elements of a semiconductor substrate, and a fan-shaped film with a cross section narrowing downward is provided on this one antioxidizing film. By implanting impurity ions as a mask and forming a field oxide film using the oxidation-resistant film as a mask, diffusion of the impurity ion-implanted especially for channel stop 2 into the device region is substantially reduced, It is possible to provide a method for manufacturing a semiconductor device that suppresses the narrow channel effect phenomenon that becomes an obstacle when producing highly integrated devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の半導体装置の製造方法を説明するだめの
構造断面図、第2図(A)〜(9)は本発明の一実施例
を説明干るだめの製造工程順に示す構造断面図、第3図
(/1)〜(C)は本発明の他の実施例を説明するだめ
の製造工程順に示す構造断面図である。 21.31・・・半導体基板、22.32・・・酸化膜
、23.33・・・耐酸化性膜(シリコン屋化1トJ)
、24.34・・・酸化膜、25・・・シリコン酸化膜
、35・・フォトレジスト、26・・・フィールド反転
防止領域、27・・・フィールド酸化膜。 出願人代理人  弁理士 鈴 江 武 彦−9= 第1図 第2図 (A)
FIG. 1 is a structural cross-sectional view of a tank explaining a conventional semiconductor device manufacturing method, and FIGS. 2 (A) to (9) are structural cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps. , and FIGS. 3(/1) to (C) are structural sectional views showing another embodiment of the present invention in the order of manufacturing steps. 21.31... Semiconductor substrate, 22.32... Oxide film, 23.33... Oxidation resistant film (Silicon shop 1 to J)
, 24.34...Oxide film, 25...Silicon oxide film, 35...Photoresist, 26...Field inversion prevention region, 27...Field oxide film. Applicant's agent Patent attorney Takehiko Suzue-9= Figure 1 Figure 2 (A)

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板の素子形成のだめの領域上方に耐酸化
性膜を設ける工程と、この耐酸化性膜上に下方に狭くな
る断面扇状膜を設ける工程と、この扇状膜をマスクとし
て不純物をイオン注入する工程と、前記耐酸化性膜をマ
スクとしてフィールド酸化膜を形成する工程とを具備し
てなることを特徴とする半導体装置の製造方法。
(1) A process of providing an oxidation-resistant film above the area where elements are to be formed on a semiconductor substrate, a process of providing a fan-shaped film with a cross section that narrows downward on the oxidation-resistant film, and using this fan-shaped film as a mask to ionize impurities. A method for manufacturing a semiconductor device, comprising the steps of: implanting; and forming a field oxide film using the oxidation-resistant film as a mask.
(2)  前記扇状膜は、耐酸化性膜上に深さ方向に狭
くなる形状のエツチング溝を有する第1の膜を形成シ7
、この第1の膜のエツチング溝に第2の膜を形成したの
ち前記第1の膜をエツチングし7て形成することを特徴
とする特許請求の範囲第1項記載の半導体装置の製造方
法。
(2) The fan-shaped film is formed by forming a first film having an etching groove that narrows in the depth direction on the oxidation-resistant film.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the second film is formed in the etching groove of the first film, and then the first film is etched.
JP18325381A 1981-11-16 1981-11-16 Manufacture of semiconductor device Pending JPS5885546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18325381A JPS5885546A (en) 1981-11-16 1981-11-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18325381A JPS5885546A (en) 1981-11-16 1981-11-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5885546A true JPS5885546A (en) 1983-05-21

Family

ID=16132433

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18325381A Pending JPS5885546A (en) 1981-11-16 1981-11-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5885546A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9405090B2 (en) 2012-07-09 2016-08-02 Mci (Mirror Controls International) Netherlands B.V. Adjusting instrument for a mirror of a vehicle

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9405090B2 (en) 2012-07-09 2016-08-02 Mci (Mirror Controls International) Netherlands B.V. Adjusting instrument for a mirror of a vehicle

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