JPS5883394A - 半導体集積回路の信号伝送方式 - Google Patents

半導体集積回路の信号伝送方式

Info

Publication number
JPS5883394A
JPS5883394A JP56179930A JP17993081A JPS5883394A JP S5883394 A JPS5883394 A JP S5883394A JP 56179930 A JP56179930 A JP 56179930A JP 17993081 A JP17993081 A JP 17993081A JP S5883394 A JPS5883394 A JP S5883394A
Authority
JP
Japan
Prior art keywords
latch
timing
signal
timing signal
phase transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56179930A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6235197B2 (OSRAM
Inventor
Seiichi Kawashima
川島　誠一
Bunichi Fujita
文一 藤田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56179930A priority Critical patent/JPS5883394A/ja
Publication of JPS5883394A publication Critical patent/JPS5883394A/ja
Publication of JPS6235197B2 publication Critical patent/JPS6235197B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Landscapes

  • Shift Register Type Memory (AREA)
  • Logic Circuits (AREA)
JP56179930A 1981-11-09 1981-11-09 半導体集積回路の信号伝送方式 Granted JPS5883394A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56179930A JPS5883394A (ja) 1981-11-09 1981-11-09 半導体集積回路の信号伝送方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56179930A JPS5883394A (ja) 1981-11-09 1981-11-09 半導体集積回路の信号伝送方式

Publications (2)

Publication Number Publication Date
JPS5883394A true JPS5883394A (ja) 1983-05-19
JPS6235197B2 JPS6235197B2 (OSRAM) 1987-07-31

Family

ID=16074409

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56179930A Granted JPS5883394A (ja) 1981-11-09 1981-11-09 半導体集積回路の信号伝送方式

Country Status (1)

Country Link
JP (1) JPS5883394A (OSRAM)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3700251A1 (de) * 1986-01-07 1987-07-09 Hitachi Ltd Verfahren und vorrichtung zur diagnose logischer schaltungen
JPS6397009A (ja) * 1986-10-13 1988-04-27 Mitsubishi Electric Corp 半導体集積回路装置
JPS63234631A (ja) * 1987-03-23 1988-09-29 Nec Corp アナログ−デジタル変換器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55163691A (en) * 1979-06-05 1980-12-19 Sony Corp Shift register

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55163691A (en) * 1979-06-05 1980-12-19 Sony Corp Shift register

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3700251A1 (de) * 1986-01-07 1987-07-09 Hitachi Ltd Verfahren und vorrichtung zur diagnose logischer schaltungen
JPS6397009A (ja) * 1986-10-13 1988-04-27 Mitsubishi Electric Corp 半導体集積回路装置
JPS63234631A (ja) * 1987-03-23 1988-09-29 Nec Corp アナログ−デジタル変換器

Also Published As

Publication number Publication date
JPS6235197B2 (OSRAM) 1987-07-31

Similar Documents

Publication Publication Date Title
KR102116274B1 (ko) 초전도 등시성 수신기 시스템
CN109074332B (zh) 用于控制输入信号路径上的等待时间的设备
US5717729A (en) Low skew remote absolute delay regulator chip
US20100090876A1 (en) Continuous synchronization for multiple adcs
JPH11316706A (ja) データ高速転送同期システム及びデータ高速転送同期方法
US8205110B2 (en) Synchronous operation of a system with asynchronous clock domains
KR101125018B1 (ko) 디지털 지연셀 및 이를 구비하는 지연 라인 회로
US4949249A (en) Clock skew avoidance technique for pipeline processors
JP2928866B2 (ja) プログラマブルなデータ転送タイミング
EP1609057A2 (en) Pipeline synchronisation device
JP2000357963A (ja) 遅延ロックループ回路
US6255878B1 (en) Dual path asynchronous delay circuit
CN101346927A (zh) 接收时钟偏斜消除的方法、设备和系统
JPS5883394A (ja) 半導体集積回路の信号伝送方式
US6633995B1 (en) System for generating N pipeline control signals by delaying at least one control signal corresponding to a subsequent data path circuit
US20040161067A1 (en) Data synchronization across an asynchronous boundary using, for example, multi-phase clocks
US20180123600A1 (en) Clock generation circuit, and semiconductor device and system using the same
US7280628B1 (en) Data capture for a source synchronous interface
US6810486B2 (en) Method and apparatus for de-skewing a clock using a first and second phase locked loop and a clock tree
WO2001016774A1 (en) A circuit design for high-speed digital communication
US5303365A (en) Clock generation in a multi-chip computer system
US6747490B1 (en) Sampling pulse generation
US4817090A (en) Integrated electronic multiplex circuit
JP3535243B2 (ja) データ転送制御用クロック同期ｃ素子群
US8707080B1 (en) Simple circular asynchronous clock domain crossing technique for digital data