JPS588334A - Input and output channel device - Google Patents

Abstract

PURPOSE:To reduce the overhead for failure processing of a program, by resetting a failure detecting state when no hindrance is given to the succession of processing when a signal failure is detected. CONSTITUTION:An unexpected IN signal selecting and controlling section 316 monitors a failure state in which a response signal operational-in is O or a signal other than address-in goes to 1. In this state, if a failure in which a failure signal goes to 1 during 2 machine cycles takes place, the failure state is detected with the control section 316 and a comparison circuit 323 and an FF325 is set. When the FF325 is set, the operation of the sequence controlling section is all once frozen. On the other hand, the frozen operation is reported to a microprogram(MP) controlling section 305, a failure processing routine of the MP is started. In this routine, a failure is discriminated as the failure due to noise on an I/O interface, the MP releases the frozen state by resetting the FF by the MP.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a main storage device (MS) and an input/output device (10).
An input/output channel device (C
Regarding H), further (: details (-, if you say, IO,!-C
Interface (IO interface) operation between H (to provide improved fault handling for various faults that occur) = Yes.

As is well known, ■0 interface control between C2, CH and ■0 is 1. According to predetermined interface operation specifications, CH and 0 are input from mutual C two-phase device, 9 interface signals are received, and the interface operation specifications (2, l! (2 refers to the state of the own device) The desired input/output operation is performed by repeating a series of processes in which a suitable response signal is sent back to the partner device and the next response signal is waited for from the partner device. By the way, CH and ■0 are connected by an interface cable (2) that passes under relatively poor conditions, such as under the floor, and during the IO interface operation, this interface signal @!In
For example, crosstalk, static electricity, etc. (2) Noise may be mixed in in a form that violates the interface operation specifications (2).
If an abnormal signal that violates 2 is detected and an abnormal signal is detected, immediately stop the 2 interface operation and report that the specified input/output operation has stopped abnormally as a program (2 pairs). When the program receives a report of this abnormal stop, it issues a retry rounding input/output branch in order to complete the desired input/output processing, but the frequency of retry processing by the program during this abnormality is high. Then,
The overhead of retry processing increases, which ultimately reduces the processing efficiency of the entire system.

In order to reduce the abnormality processing overhead for the above program (2), the present invention provides
Among failures on the interface, if the CH determines that the failure is of a type that does not impede the continuation of normal IO interface operation, the IO interface operation is stopped and the problem is not reported to the program. , provides a CH that can reset the failure state and continue normal interface processing.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a part related to a sequence control section that performs CH IO interface control according to the present invention, and FIG. 2 is a diagram showing the correspondence between CH sequence control and IO interface signals.

Now, before instructing the IO to start, the microprogram (hereinafter referred to as MP) control unit 305, which oversees and controls the flow of CH processing, inputs the IO number to be the target of the input/output operation and the input/output operation target. A command specifying the type is sequentially sent to the output register 30 via the out bus 306.
7,308+ faked. At this point, the IO number set in the output register 307 is BUS/OU
It is sent to the IO 326 via the T 310, and the state of ■ in FIG.
= MP control unit 3-05 sends a sequence code register (hereinafter abbreviated as SC) to the CH sequence control unit (sequence code register (hereinafter abbreviated as SC) as an activation instruction to a pair of IOs via an out bus 306).
301, a code (SEQ C0DE
) is set to 1011. This corresponds to the state of ■ in the s2 diagram (2).The phase counter (hereinafter abbreviated as PC) 302 and the cycle counter (hereinafter abbreviated as CC) 303 are reset to (=@0'') at the same time as the SC set. Thereafter, CC 303 is incremented by 1 every machine cycle by C0UNTER control unit 314 until WAIT latch 313 is set.

Sequence control is a control system that sequentially performs predetermined processes only when predetermined conditions (predetermined for each sequence) are satisfied.In the embodiment of the present invention, 8C=01. The 7-ken of PC=OO is BUS
0UT3101 IO number that has been falsified
326 to the logical (signal ADR0UT for sending two
(address out), 5EL-OUT (select
This is defined as a sequence for setting HLDOUT (hold out) and HLDOUT (hold out). 5C3
Each output signal of 01 and PC302 is input to a decoder 304 (2), and when this decoder 304 recognizes 8C=01 and PC=oo, it outputs a signal S1 indicating the logical product of 5c-ol and PC=OO as an OUT signal. The output signal of the CC 303 is also input to the 0tJT signal control unit 3151, and the 0UTI signal control unit 315 takes the AND condition of the output signal S1 of the decoder 304 and the output of the CC 303, Output tag register (OUT T
AGREG) 320 OUT TAG signal. That is, due to the conjunction condition C2 of Sl and CC-01, A
The DROUT signal is set, and the AND condition of Sl and CC=02 (=Therefore, the 8gLOUT signal and HLDOUT signal are set. This corresponds to the state of O in FIG. 2 (;).

The output signal S1 of the decoder 304 is also input to the WAIT control unit 318, and the WAIT control unit 318 sets the WAIT latch 313 according to the AND condition of Sl and CC=02. The state in which is set indicates that the CH is waiting for a signal response from the IO, and the
14: The +1 operation of CC 303 is suppressed.

Furthermore, the second C0UNT'ER control unit 314
PC302 from @00” to '01 with the AND condition of =2
'E Update. This pc-oi sequence is IO
This is a sequence of waiting for the response signals OPI and IN (operational in) expected by the CF to rise, and the WAIT latch 313 remains set until the IO and JJOPL IN signals rise. , CH perform no operation.

In such a state, the decoder 304 outputs 5C=01
and PC=01, and this signal is sent to the expected IN signal selection control section 317, the non-expected IN signal selection control section 316, the OUT signal control section 315,
C0UNTER control unit 314 and W input IT control unit 318
1": Input. The expected IN signal selection control unit 317 selects the signal S1 so that only the OPL IN signal is expected (
= A signal is input manually to the comparison circuit 322, and O from IO
The PL IN signal is input to the input register (IN TAG BEG
) 321 (n is set, and (2 comparison circuits 32
21”: Waiting for input.

OPL INI number from IO and 0P from control unit 317
If the signals expecting LIN match, the comparator circuit 322 sets the match detect circuit 324. The output signal of the flip-flop 324 is sent to the WAIT circuit 3.
18: The AND condition of 1sl, PC=01'' and cc=OO (reset the WAIT latch 313 from 2).

WAIT latch 313 is reset and C0U
The NTER control unit 314 starts operating, and the CC 303 becomes 1.
+1 per cycle. Then, the AND condition of S2 and CC=1 (from the second, AD of OUT TAG rule 320
ROUT is reset, and the output register 307 no longer sends out the C2+IO number on BO20UT310.

This sequence fi (SC=01, PC=01) (=
In this case, the signal from IO that CH expects is OPL I
N, and no input tag signals from the other 10 are expected. In the unexpected IN signal selection control unit 3161 to which 82 signals indicating this sequence are input, 0PL
A signal indicating that a signal from an IO other than IN is not expected is input to the comparison circuit 323, and if an unexpected signal comes from the temporary 1-N O, the unexpected signal detection flip 70 block is input from the comparison circuit 323C-. Set 325.

To explain the processing of each of the other sequences in Figure 2 (2), in the sequence where the AND condition of 5C=01 and PC=02 is satisfied, the command waits for the address in (ADRIN) signal to come from IO,・Out (CMD 0U
T) Sends a signal.

In a sequence in which the AND condition of 8C=01 and PC=03 is satisfied, CMD OUT is reset after waiting for ADRIN to be input from IO to 7).

Now, in sequence 8C-01/PC=02, among the human tag signals from IO, OPL IN maintains the state of @1m, and the new (:human DkLIN signal is expected to become "1-1"). This is a sequence in which the non-scheduled IN signal selection control unit 316 monitors an abnormal state in which OPL IN becomes 101 or a signal other than AI) RIN becomes @i'c.In this state (=2, As shown by the broken line in FIG. 2, when an abnormal state occurs in which the abnormal signal STA IN is 11'' during two machine cycles, the abnormal state is caused by the unexpected IN signal selection control unit 316 and the comparison circuit 32.
3 (2), and the flip-flop 325 is set. When the flip-flop 325 is set, all operations of the sequence control section are frozen for once.

On the other hand, when an abnormality is detected and the frozen operation is reported to the MP control unit 305 (2), the MP failure handling routine starts running, and in this failure handling routine, a simple noise on the IO bay interface ( = If it is determined that there is an abnormality (for example, it is determined that the abnormal signal has already recovered), the MP resets the flip-flop 325. C: Therefore, the frozen state is released and a failure is detected. Proceed with the process as if it were Shinakatsuku.

In this way (2. Clearing the fault detection state even after a fault has been detected (2), it is possible to continue processing as if there was no fault.
The hardware ensures that the noise on the IO bay interface does not affect other CH processing units (2) in a way that actively continues CH processing, and the M P l
': That it was possible to inform about this to C.
: If it is something that can be realized more easily, such as a parity error on BUS IN, and if it is of such a nature that processing cannot be continued ignoring the failure, the CH needs to abort the process and report it to the program. There is.

As explained above, according to the present invention, a failure such as noise is induced on the IO interface, and the failure actively inhibits the normal progress of 7.-ware processing. The hardware itself guarantees that the problem is not detected (=Therefore, there is no need to report a failure for program C, and the overhead of program retries and the like can be reduced).

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a CH
FIG. 2 is a diagram showing the correspondence between frame control and the 0 interface signal. 301...Sequence code register, 302...
... Phase counter, 303 ... Cycle counter, 304 ... Decoder, 307.308.
...Output register, 313...WAIT latch, 32
o...Output tag register, 321...Input tag register, 322゜323...Comparison circuit, 324...Coincidence detection flip-flop, 325...Unexpected signal detection 7o lip-flop, 326...■ 0 device.

Claims (1)

[Claims] 1. In the human output channel device that controls data transfer between the main storage device and the input/output device, a predetermined interface specification C 2. Accordingly, detect a failure in the signal received in response from the input/output device side. means to detect the failure, determine whether it is a failure to ensure that the normal processing of the channel itself will not be disturbed, and continue processing I: Do not ignore the failure; means for resetting the fault detection state when it is determined that