JPH0381835A - Information processor - Google Patents

Abstract

PURPOSE:To effectively detect and correct a bit error in an instruction code and to execute an aimed instruction by finding out an instruction code minimizing its inter-code distance between plural previously set instruction codes and an inputted instruction code. CONSTITUTION:When an instruction code X is inputted to a CPU and can not be interpreted, the error correction processing of the inputted instruction code is started. An instruction code group memory is referred and the inter-code distances between the inputted instruction code and respective previously set instruction codes A to D are found out.Then the found inter-code distances are mutually compared and the instruction code B positioned on the shortest distance 4 is found out and the code B is substituted for the code X to correct a bit error. Consequently, the bit error of the inputted instruction code X can be simply and efficiently corrected and the instruction aimed by the code X can be effectively executed.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention provides information processing that can effectively correct errors in input instruction codes and execute instructions intended by the input instruction codes. Regarding equipment.

(Prior Art) An instruction code of an information processing device is composed of fields corresponding to an instruction, and the instruction is specified by giving a specific value to this field. Normally, one code is associated with one instruction unless special consideration is given to the above field. Although it depends on the definition of the field value, generally speaking, if the code differs by even one bit, it will be interpreted and executed as a completely different instruction from the intended instruction.

Conventionally, this type of instruction code is generally classified and assigned according to one instruction system. For this reason, relatively similar instruction codes are often assigned to multiple instructions belonging to the same architecture group. For this reason, it has been almost impossible to deal with bit errors in instruction codes.

By the way, in data transfer, there is a technology that attaches a parity code to a series of transferred data such as instruction codes, and uses this parity code to perform a parity check to detect and correct bit errors in the transferred data. . However, for this parity check, it is necessary to add a special code called a parity code, and as the number of bits targeted for error detection and correction increases, it is necessary to use many parity codes. There is a problem with this.

For this reason, it has been virtually impossible to introduce the idea of correcting errors in instruction codes by parity checking into the internal processing of information processing devices.

(Problem to be Solved by the Invention) As described above, in conventional information processing devices, it is virtually impossible to correct bit errors in instruction codes used internally, and instruction codes with bit errors are If this happens, there is a problem in that an incorrect command will be executed accordingly.

The present invention has been developed in consideration of these circumstances, and its purpose is to efficiently detect and correct bit errors in instruction codes and to provide a highly practical method that can execute intended instructions. The purpose of the present invention is to provide an information processing device.

[Structure of the Invention] (Means for Solving the Problems) The information processing device according to the present invention has the following features: ■ A plurality of instruction codes used therein are determined by their inter-code distance, for example, the number of bits with different signs of corresponding bits. The Hamming (HamIling) distance defined by is determined to be sufficiently far from each other, and ■ When the input instruction code cannot be interpreted, the above-mentioned instruction codes are determined such that the inter-code distance is sufficiently far from each other as described above. The inter-symbol distance from each input instruction code is determined, and the manually-operated instruction code is corrected to an instruction code with the shortest inter-symbol distance, and the instruction code is interpreted and the instruction is executed. It is something to do.

(Function) According to the present invention, since each of a plurality of instruction codes is predetermined to have a sufficient inter-code distance from other instruction codes, when an input instruction code cannot be interpreted, the input It interprets the instruction code as having a bit error, and performs error correction by treating the instruction code with the shortest inter-symbol distance as the input instruction code before the bit error occurs. , the bit error can be effectively corrected without using redundant codes such as codes.

In other words, in a highly reliable system, the number of bit errors is assumed to be small, and the error correction is performed by treating the instruction code with the shortest inter-symbol distance as the original input instruction code. It becomes possible to effectively execute the command intended by the input command code.

(Embodiment) Hereinafter, an information processing apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the concept of the instruction code used in the device of the embodiment. Here, the instruction code has a field structure of 11 bits, A, B, and C.

An example is shown in which four instructions D are assigned such that the inter-code distances between them are sufficiently large.

Here, the intersymbol distance defined as the Hamming distance is 2
It is defined as the number of bits with different signs between corresponding bits between two instruction codes, and in this example, the inter-symbol distance between instruction codes in which all 11-bit codes are different is the maximum [inter-symbol distance: 11] is defined as

In the example shown in FIG. 1, the instruction code A [00000000000F instruction code D [11111111111] is an instruction that takes the maximum inter-symbol distance. Similarly, the inter-symbol distance of instruction code B [01010101010] and instruction code C [101010101011 is also the maximum.

Therefore, the above instruction code B has an inter-symbol distance of [5] with respect to instruction code A, and an inter-symbol distance of [6] with respect to instruction code D, and is sufficient for each of these instruction codes A and D. It is decided that you should leave. Furthermore, regarding the above instruction code C, assuming that the inter-symbol distance for instruction code A is [6] and the inter-symbol distance for instruction code D is [5], it is sufficient for each of these instruction codes A and D. It is decided that you should leave.

In other words, the four instruction codes A, B, C, and D are determined so that the distance between the codes is sufficiently large.

By the way, after instruction codes A and D are defined, if instruction code B is set with the consideration that the distance between codes will be sufficiently large only for instruction code A, then instruction code B will be different from instruction code D. The inter-symbol distance is the shortest due to a difference of 1 bit. Therefore, instruction code B is determined so that the inter-symbol distance is sufficiently large for each of instruction codes A and D, and the next instruction code C is determined so that the inter-symbol distance is maximized with respect to instruction code B.

This kind of instruction code assignment is determined by the number of bits that make up the field and the number of instructions, but basically the two instructions whose code distance is maximum (the number of bits that make up the field) After the codes are defined, the next instruction code pair is defined at a position approximately equidistant from these next instruction codes and has the maximum inter-code distance.

This device uses multiple instruction codes defined in this way and sequentially executes instructions indicated by the input instruction codes.
For example, it is configured with an error correction function as shown in FIG.

In FIG. 2, the instruction code group memory 2 stores instruction codes defined as described above.
For example, it is given as ROM data.

The information processing unit (CPU) manually interprets (decodes) the input command code given as the program progresses in step a)S. If the input instruction code cannot be interpreted (step b), this is detected and error correction processing for the input instruction code is activated.

This error correction process is performed by referring to the instruction code group memory Z described above and determining the inter-symbol distance between the manual instruction code and each preset instruction code (step C). This inter-symbol distance is calculated by checking whether the codes of corresponding bits match or differ, and determining the number of bits with different codes.

The inter-symbol distances for each instruction code thus determined are compared with each other, and the instruction code located at the shortest distance among them is determined (step d).

Incidentally, if a plurality of instruction codes are found as instruction codes located at the position of the shortest inter-symbol distance, error processing is executed as described later.

When the instruction code at the shortest inter-symbol distance position is obtained as described above, the input instruction code is replaced with this instruction code to correct its bit error (step e).

The error-corrected instruction code is interpreted in this way and the instruction is executed. In practice, the instruction code intended by the input instruction code that caused the bit error is determined as the instruction code located at the shortest inter-symbol distance position, and the instruction code is interpreted accordingly. According to the selection result in , the instruction intended by the instruction code is executed as is.

To specifically explain the instruction code correction process mentioned above,
For example, assume that the input instruction code is given as instruction food X [000101001111, as shown in FIG. In this case, since this input instruction code X does not correspond to any of the instruction codes A, B, C, and D defined as described above, it is interpreted that a bit error has occurred. As a result, the inter-symbol distances between the input instruction code X and the instruction codes A, B, C, and D are calculated, and in this case, the inter-symbol distance XA; 5. Inter-symbol distance XB; 4 Inter-symbol distance XC; 7. The intersymbol distance XD; 6 is obtained. By comparing these inter-code distances with each other, the shortest inter-code distance [4] is found, and it is estimated that instruction code B that takes this shortest inter-code distance has become input instruction code X due to a bit error. Ru. Then, according to this estimation result, 4 bits in the manual instruction code X are corrected,
Correct this to instruction code B.

On the other hand, as shown in FIG. 4, when the instruction code in which a bit error occurs is given as instruction code Y [101010000001, the instruction codes A, B.

The inter-symbol distance between C and D is the inter-symbol distance XA, 3. The inter-symbol distance XB, 8 is calculated as the inter-symbol distance XC, 3, and the inter-symbol distance XD, 8, respectively. However, in this case, since two instruction codes with the shortest inter-symbol distance are required, it is not possible to determine which of them has caused a bit error and has been given as the input instruction code Y. Therefore, in such a rare case, the bit error cannot be corrected as is, so error processing is performed, such as presenting these commands to the operator and prompting the operator to select one. Or,
If there is an error, process the error as an uncorrectable code.

Thus, according to this device that performs correction processing for bit errors in input instruction codes, the bit errors can be effectively corrected without using special codes as seen in parity checks. It is possible to correct the instruction and execute the instruction intended by the input instruction code.Furthermore, as shown in the example above, it is possible to deal with a large number of bit errors depending on the inter-symbol distance of multiple instruction codes. It is possible to effectively correct bit errors within the bit range within the intersymbol distance of each instruction code.As a result, in information processing that requires reliability, malfunctions caused by bit errors in input instruction codes can be corrected. This makes it possible to significantly reduce the occurrence of errors and increase the reliability of the processing operations.

Furthermore, according to the present device which functions as described above, from another point of view, it is also possible to specify one instruction with a plurality of instruction codes. As a result, for example, by associating a plurality of instruction codes with short inter-code distances with an instruction, it is possible to make one process correspond to a data group within a processing range.

Note that the present invention is not limited to the embodiments described above. For example, the number of bits of an instruction constituting one field is determined according to its specifications, and the instruction code assigned to it may be determined according to the number of instructions. In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As explained above, according to the present invention, a plurality of instruction codes are determined so that the inter-code distance between them is sufficiently large, so that bit errors within the inter-code distance range are effectively suppressed. This makes it possible to detect and correct information. As a result, it is possible to easily and efficiently correct bit errors in an input instruction code and effectively execute the instruction intended by the input instruction code, which has great practical effects. .

[Brief explanation of drawings]

The figures show an information processing device according to an embodiment of the present invention. FIG. 1 is a diagram showing an example of an instruction code used in the embodiment device, and FIG. 2 is a diagram showing a bit error in a manual instruction code in the embodiment device. FIGS. 3 and 4 are diagrams illustrating an example of a correction process procedure, and are diagrams each illustrating a specific example of a bit error in an input instruction code in the apparatus of the embodiment. A, B, C, D...instruction code, X, Y...input instruction code that caused a bit error, 2...instruction code group memory.

Claims (1)

[Claims] In an information processing device that interprets an input instruction code and executes processing assigned to the instruction code, the input instruction When a code cannot be interpreted, the inter-code distances between the plurality of instruction codes and the input instruction code, which are set so that the inter-code distances are sufficiently far from each other, are determined, and the instruction code with the shortest inter-code distance is selected. An information processing device comprising means for correcting an input instruction code and interpreting the instruction code.