JP7364263B2 - Multiplexing circuit device and error recovery method - Google Patents

Description

The present invention relates to a multiplexing circuit device and an error recovery method.

In order to suppress the occurrence of SEU (Signal Event Upset: Soft Error) in FPGA (Field Programmable Gate Array) devices, it is necessary to prepare equipment and environments that physically block neutron beams. However, devices may be used in places where such facilities and environments are not available. Therefore, in order to deal with SEU, manufacturers of FPGA devices provide circuits that detect and repair the occurrence of SEU. The reliability of FPGAs is ensured through the use of such circuitry provided by the manufacturer and through the multiplexing of user circuits or the device itself.

On the other hand, there is a programmable device with improved SEU resistance (for example, see Patent Document 1). When this programmable device compares outputs from redundant circuits and detects the occurrence of an error, it reconfigures the circuit in which the error has occurred. Further, the programmable device inputs the internal state of the circuit in which no error occurred to the reconfigured circuit.

International Publication No. 2013/027482

Detection of SEU takes a certain amount of time. In recent years, as the capacity of FPGA devices has increased, the time required to detect SEUs has also tended to increase. If the time required for detection is long, it becomes difficult to detect and repair errors when SEUs occur frequently. This leads to reduced reliability of the device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiplexing circuit device and an error recovery method that can solve the above-mentioned problems.

According to the first aspect of the present invention, the multiplexing circuit device sets a part of the calculation results in each of the plurality of multiplexed circuits as a check range, and checks the occurrence of an error in the check range. Obtain check results for a plurality of intermediate check circuits and a plurality of different check ranges of each of the plurality of circuits from the plurality of intermediate check circuits, and determine whether or not there is an error in the circuit based on the obtained check results. and a restoring means for restoring data of the error generating circuit, which is the circuit determined to have an error by the determining means.

According to the second aspect of the present invention, the error repair method uses a part of the calculation results in each of a plurality of multiplexed circuits as a check range, and an intermediate step for checking the occurrence of an error in the check range. a checking step; a determining step of acquiring check results from the intermediate checking step for a plurality of different check ranges of each of the plurality of circuits, and determining whether or not there is an error in the circuit based on the acquired check results; and a repair step of repairing the data of the circuit determined to have an error in the determination step.

According to the present invention, it is possible to shorten the time from occurrence of SEU to recovery in a circuit.

1 is a diagram showing the configuration of an FPGA according to an embodiment of the present invention. FIG. 3 is a flow diagram showing the operation of the FPGA according to the embodiment. It is a figure explaining the effect by the same embodiment. FIG. 2 is a diagram showing the minimum configuration of a multiplexing circuit device according to the same embodiment.

Embodiments of the present invention will be described in detail below with reference to the drawings.

This embodiment shortens a series of recovery times from the occurrence of a soft error (SEU) in a programmable device to SEU detection check, data recovery, replacement with normal data, and data recovery. This improves the reliability of a system equipped with programmable devices. In this embodiment, in order to shorten the time from the occurrence of SEU to recovery in a programmable device, attention is paid to the time required to detect SEU and the time to recover data. In the following, a case where the programmable device is an FPGA will be described as an example.

The user circuit of the FPGA of this embodiment implements a multiplexing circuit. The multiplex circuit has multiple functional circuits. A functional circuit is a circuit that implements arbitrary functions such as various calculations and control. The FPGA of this embodiment performs SEU detection for the entire device and SEU detection for each functional circuit as a whole. Any technique can be used for these SEU detections. For example, any existing SEU detection technique may be used.

In the FPGA of this embodiment, each multiplexed functional circuit is provided with a plurality of intermediate check circuits. In addition to the above SEU detection, the FPGA uses an intermediate check circuit to perform intermediate checks as needed. The intermediate check is a check on a limited range of data among the calculation result data in the functional circuit. A plurality of intermediate check circuits within one functional circuit each check different ranges of data.

The FPGA uses the check results in each intermediate check circuit of each functional circuit to check the presence or absence of an error, the functional circuit in which the error has occurred, and the approximate location where the error has occurred. The FPGA performs a partial check of the functional circuit based on the results of the investigation. Partial checking is error checking performed by limiting the checking range rather than checking the entire functional circuit. For error checking, CRC (Cyclic Redundancy Check), ECC (Error-Correcting Code), etc. can be used. By limiting the check range, it is possible to shorten the detection time required to detect errors. When the FPGA detects an error, it repairs the data of the functional circuit in which the error has occurred. Specifically, the FPGA repairs configuration data stored in CRAM (Configuration Random Access Memory) of the functional circuit. Any technique can be used for this repair. For example, any existing SEU countermeasure circuit may be used.

After the functional circuit is repaired, the FPGA of this embodiment partially copies the data of the calculation result from the normally operating functional circuit. The FPGA performs this partial copy multiple times until no errors occur. As a result, the FPGA recovers the data of the calculation result of the functional circuit in which the error occurred. Therefore, in the FPGA of this embodiment, there is no need to reset the entire circuit to recover data after CRAM repair.

The SEU countermeasure circuit provided by the FPGA device manufacturer is capable of detecting and repairing errors in the configuration memory of the FPGA. However, it was difficult to restore user circuit data while operating the system. Therefore, when an SEU occurs, the circuit is reset. For this reset, it was necessary to temporarily stop the circuit or the device itself equipped with the circuit. For example, in the technique disclosed in Patent Document 1, after reconfiguring a circuit in which an error has occurred, the reconfigured circuit does not operate and stops until the internal state of the circuit in which no error has occurred is input to the reconfigured circuit.

The FPGA of this embodiment performs intermediate checks multiple times while checking the entire circuit and each multiplexed functional circuit during operation. Even when an SEU occurs, the FPGA of this embodiment copies the data of the normal functional circuit to the functional circuit in which the error has occurred, without stopping the normally operating functional circuit. Therefore, the FPGA of this embodiment can recover from SEU without stopping its operation.

FIG. 1 is a diagram showing the configuration of an FPGA 1 according to an embodiment of the present invention. In the figure, only the configurations related to this embodiment are extracted and shown. FPGA1 is an example of a multiplexing circuit device. The FPGA 1 includes a user circuit 2, an error determination circuit 6, partial check circuits 7-1 to 7-N (N is an integer of 3 or more), a soft error countermeasure circuit 8, and a data copy circuit 9. When partial check circuits 7-1 to 7-N are collectively referred to, or when any one of them is not specified, they are referred to as partial check circuit 7.

The user circuit 2 includes functional circuits 3-1 to 3-N and a majority circuit 5. When the functional circuits 3-1 to 3-N are collectively referred to, or when any one of them is not specified, they are referred to as the functional circuit 3. Functional circuits 3-1 to 3-N are the same circuit. The functional circuits 3-1 to 3-N and the majority circuit 5 constitute a multiplexing circuit.

The functional circuit 3 is a circuit that implements arbitrary functions such as various calculations and control. Configuration data for realizing the functions of the functional circuit 3 is stored in the CRAM. In order to quickly detect an SEU occurring in the CRAM, the functional circuit 3 includes K (K is an integer of 2 or more) intermediate check circuits 4. The intermediate check circuit 4 is provided for each arbitrary circuit block or stage within the functional circuit 3. The intermediate check circuit 4 corresponding to the kth (k is an integer from 1 to K) circuit block or stage in the functional circuit 3-n (n is an integer from 1 to N) is converted into an intermediate check circuit 4-n-k. It is written as The intermediate check circuit 4-nk performs an intermediate check to check intermediate calculation results in a series of calculations performed by the functional circuit 3-n. Specifically, the intermediate check circuit 4-nk performs parity on the intermediate calculation results. Alternatively, the intermediate check circuit 4-nk corresponds to the intermediate calculation result of the functional circuit 3-n and another functional circuit 3-n' (n'≠n, n' is an integer between 1 and N). Errors are detected by comparison with intermediate calculation results.

The majority circuit 5 determines the correct operation result from among the operation results of each of the functional circuits 3-1 to 3-N by majority vote, and outputs the determined operation result.

The error determination circuit 6 determines the presence or absence of an error, the functional circuit 3 in which the error has occurred, and the estimated error location based on the intermediate check results in each intermediate check circuit 4 of each functional circuit 3. The estimated error location is the approximate location where the error occurs. For example, the estimated error location is a range that is estimated to include the location where an error has occurred. For example, when the intermediate check circuit 4-nk detects an error, the error determination circuit 6 determines that an error has occurred in the calculation of the k-th circuit block or stage. In other words, the error estimation location is the location where the intermediate check circuit 4-nk performs the calculation to obtain the calculation result targeted for the intermediate check. If the intermediate check result of the intermediate check circuit 4-nk is an error, the error determination circuit 6 informs the partial check circuit 7-n that there is an error, that there is an error in the functional circuit 3-n, and that the functional circuit 3-n The estimated error location is reported to the other partial check circuits 7-n', and the absence of errors is reported to the other partial check circuits 7-n'. Furthermore, the error determination circuit 6 reports to the data copy circuit 9 the presence of an error, the error in the functional circuit 3-n, and the estimated error location in the functional circuit 3-n. If no error is detected in any of the intermediate check circuits 4, the error determination circuit 6 reports no error to the partial check circuits 7-1 to 7-N and the data copy circuit 9.

One partial check circuit 7 is implemented for each functional circuit 3. Partial check circuit 7-n corresponds to functional circuit 3-n. Each partial check circuit 7-n normally cycles through and checks the CRC or ECC (hereinafter referred to as CRC/ECC) of the functional circuit 3-n. When the partial check circuit 7-n receives a report from the error determination circuit 6 that there is an error in the intermediate check, the partial check circuit 7-n stops the normal circuit and starts a partial CRC/ECC check of the functional circuit 3-n. The target of the CRC/ECC partial check is the portion of the functional circuit 3-n where the error is estimated. When the intermediate check circuit 4-n detects a CRC/ECC error, it reports the bit position where the error has occurred to the soft error countermeasure circuit 8.

The soft error countermeasure circuit 8 normally performs a CRC/ECC check on the entire device, and when an error is detected, repairs the bit at the bit position where the error is detected. Similarly, when the soft error countermeasure circuit 8 receives a report from the partial check circuit 7 of the bit position of the functional circuit 3 where an error has occurred, it repairs the bit at the reported bit position. The soft error countermeasure circuit 8 restores the configuration data stored in the CRAM by replacement or correction. In the case of replacement, the soft error countermeasure circuit 8 reads the bit stream stored in the external memory 10 and sets the bit at the position where the error is detected. In the case of correction, the soft error countermeasure circuit 8 repairs the bit in which an error has occurred using ECC. When the recovery is completed, the soft error countermeasure circuit 8 reports the completion of the recovery to the data copy circuit 9. Note that as the soft error countermeasure circuit 8, any SEU countermeasure circuit that restores the configuration data stored in the CRAM can be used.

The data copy circuit 9 receives a report from the error determination circuit 6 about the presence or absence of an error in the functional circuit 3, the functional circuit 3 in which the error has occurred, and the estimated error location. Furthermore, upon receiving a report of completion of recovery from the soft error countermeasure circuit 8, the data copy circuit 9 performs a partial copy of the calculation result. That is, the data copy circuit 9 copies the data of the operation result stored in the register corresponding to the estimated error location from the functional circuit 3-n' where no error has occurred, and copies the data of the operation result stored in the register corresponding to the estimated error location from the functional circuit 3-n' where the error has occurred. Set to the corresponding register. The data copy circuit 9 performs this partial copy at the falling edge of the operating clock of the user circuit 2 or at twice the clock. The data copy circuit 9 repeats partial copying multiple times until there are no more error reports from the error determination circuit 6. When there are no more error reports from the error determination circuit 6, the data copy circuit 9 assumes that the data of the repaired functional circuit 3 has been restored and has been restored, and stops partial copying. Note that the data copy circuit 9 may determine that there are no more error reports when all the calculation results output from each functional circuit 3 to the majority circuit 5 match.

FIG. 2 is a flow diagram showing the operation of the FPGA 1 in FIG. 1. The FPGA 1 performs the operation shown in FIG. 2 while the user circuit 2 is operating. Note that the functional circuit 3-n is also referred to as a functional circuit #n.

The soft error countermeasure circuit 8 repeatedly performs a CRC/ECC check on the entire device of the FPGA 1 (step S101). On the other hand, in the user circuit 2, each intermediate check circuit 4 of each functional circuit 3 performs an intermediate check on the calculation result for each block or stage. All or some of the plurality of intermediate check circuits 4 perform intermediate checks in parallel. The error determination circuit 6 monitors the calculation results of intermediate checks in each intermediate check circuit 4 and determines whether an error has occurred (step S102).

When the error determination circuit 6 determines that there is no error in the intermediate check (step S102; NO), it reports the absence of an error to the partial check circuits 7-1 to 7-N and the data copy circuit 9. The partial check circuits 7-1 to 7-N repeatedly perform CRC/ECC checks on the functional circuits 3-1 to 3-N (steps S103-1 to S103-N). That is, each partial check circuit 7-n performs a CRC/ECC check by circulating within the functional circuit 3-n.

On the other hand, when the error determination circuit 6 determines that a soft error has occurred in the intermediate check circuit 4 of any of the functional circuits 3 (step S102; YES), it performs the process of step S104. That is, the error determination circuit 6 identifies the approximate location where the error occurred in the functional circuit 3-n based on the intermediate check circuit 4-nk whose intermediate check result was an error (step S104). The error determination circuit 6 outputs an error occurrence report to the partial check circuit 7-n and the data copy circuit 9 (step S105). The error determination circuit 6 determines, based on the error occurrence report, the occurrence of an error, the functional circuit 3-n or intermediate check circuit 4-nk where the error was detected, and the estimated error location indicating the approximate location where the error occurred. Notify. Further, the error determination circuit 6 reports no error to the partial check circuits 7-n' other than the partial check circuits 7-n. When the partial check circuit 7-n' receives a report of no error, it continues the CRC/ECC error check by regular circulation.

When the partial check circuit 7-n receives the error occurrence report, it stops the normal CRC/ECC error check and performs CRC/ECC on a part of the functional circuit 3-n corresponding to the estimated error location. A partial check is performed (steps S106-1 to S106-N). When the partial check circuit 7-n detects a CRC/ECC error, it reports the bit position where the error was detected to the soft error countermeasure circuit 8.

The soft error countermeasure circuit 8 detects soft errors in the CRC/ECC check in step S101, the CRC/ECC check in steps S103-1 to S103-N, or the CRC/ECC partial check in steps S106-1 to S106-N. is detected (step S107). If the soft error countermeasure circuit 8 determines that no error has been detected in any of the processes (step S107: NO), the process returns to the first process.

On the other hand, if the soft error countermeasure circuit 8 determines that a soft error has been detected in any one (step S107: YES), it determines the repair method instructed by the user (step S108). The user's instructions are set in the FPGA 1 in advance. When the user's instruction is to replace the CRAM, the soft error countermeasure circuit 8 replaces the configuration data of the CRAM of the functional circuit 3-n in which the error has occurred with the corresponding data of the bit stream stored in the memory 10. (Step S109). After the replacement, the soft error countermeasure circuit 8 outputs a replacement completion report to the data copy circuit 9. When the user's instruction is to correct an error bit, the soft error countermeasure circuit 8 performs ECC, etc. on the data at the bit position where the error occurred in the CRAM of the functional circuit 3-n using the data in the functional circuit 3-n. (Step S110). After the correction, the soft error countermeasure circuit 8 outputs a repair completion report to the data copy circuit 9.

The data copy circuit 9 receives from the error determination circuit 6 whether or not there is an error, and if there is an error, reports the functional circuit 3-n or intermediate check circuit 4-nk where the error was detected and the estimated error location. receive. Further, upon receiving a replacement completion report or a repair completion report from the soft error countermeasure circuit 8, the data copy circuit 9 transfers some calculation result data from the functional circuit 3-n' in operation where no error has occurred. A partial copy is made to the functional circuit 3-n (step S111). At this time, the data copy circuit 9 copies the data in the range corresponding to the estimated error location reported from the error determination circuit 6 from the functional circuit 3-n' in operation where no error has occurred. The data copy circuit 9 repeats this partial copy multiple times at the falling edge of the operating clock of the user circuit 2 or at a clock that is twice or more faster until the error is resolved (step S112). The data copy circuit 9 determines that the error has been resolved when it receives a report from the majority circuit 5 that all the calculation results of the functional circuits 3 match. Alternatively, the data copy circuit 9 determines that the error has been resolved when the error determination circuit 6 determines that there is no error. In this way, the data copy circuit 9 repeats the partial copy in step S111 a plurality of times, and determines whether the recovery is completed based on whether or not there are no more error reports. When the data copy circuit 9 determines that the recovery is complete, it finishes copying the data to the functional circuit 3-n where the error occurred.

FIG. 3 is a diagram for explaining the effects of this embodiment. FIG. 3 shows a comparison of times related to a series of operations from soft error occurrence to detection and recovery. FIG. 3 shows an example in which the functional circuits of the FPGA are tripled and the error correction method is restoration. The FPGA to which this embodiment is not applied (hereinafter referred to as related FPGA) performs error checking by circulating the entire triplexed circuit. When the associated FPGA detects an error, it repairs the error and resets the entire logic to match the data at the repaired location with the data in other functional circuits. Before the entire logic is reset, the related FPGA is operating as a duplex circuit due to an error in one of the triplex circuits. Then, during the reset, the logic of the multiplexing circuit of the associated FPGA or the system using the associated FPGA is stopped, and the triplexing is restored after the reset.

On the other hand, the FPGA 1 of this embodiment performs a cyclic check of the entire circuit and each functional circuit 3, and furthermore, the intermediate check circuit 4 performs a partial check of CRC/ECC. Therefore, the FPGA 1 may detect an error in the intermediate check circuit 4-1-4 while, for example, cycling through and checking the first functional circuit 3-1. The FPGA 1 of this embodiment repairs the configuration data of the functional circuit 3-1, and after the restoration, is part of the calculation results of the functional circuits 3-2 and 3-3 that continue to operate in a duplex manner. Copy partial data. Since the functional circuits 3-2 and 3-3 continue to operate while partial data copying is being performed, the FPGA 1 operates in duplex mode until the partial copy is completed, and then operates in triple mode after the partial copy is completed. will be revived. Therefore, the FPGA 1 of this embodiment can reduce duplex operation time and downtime compared to related FPGAs.

According to the present embodiment, the configuration device shortens the error detection time of multiplexed circuits, and further performs data recovery of calculation results by partial copying. Therefore, the time required for recovery is significantly shorter than with conventional configuration devices. Furthermore, since there is no need to reset the circuit or system, it contributes to improved system reliability.

The soft error rate of CRAM is decreasing with the miniaturization of technology and the adoption of FinFFT (Fin Field-Effect Transistor). On the other hand, since the CRAM capacity of FPGA devices is increasing, the soft error occurrence rate tends to increase as a result. Although there are various SEU countermeasures, there are some countermeasures for equipment that is used in environments where there is a high probability of being hit by neutron beams, equipment that takes into account cases in which it occurs frequently even in environments where the probability of being hit by neutron beams is low, or non-stop, mission-critical equipment. is necessary. The FPGA of this embodiment is suitable for information devices such as computers, servers, IoT devices, and in-vehicle devices that require reliability and non-stop operation, as well as information devices that are required to operate in environments with many neutron beams. Particularly useful. Note that these are merely examples, and the application of the FPGA of this embodiment is not limited to these.

FIG. 4 is a diagram showing the minimum configuration of the multiplexing circuit device 100 according to the embodiment of the present invention. The multiplexing circuit device 100 includes a plurality of N multiplexed circuits 110 (N is an integer of 3 or more), a determination circuit 130, and a repair circuit 140. The N circuits 110 are respectively written as circuits 110-1 to 110-N. Each circuit 110 has K intermediate check circuits 120 (K is an integer of 2 or more). The K intermediate check circuits 120 included in the circuit 110-n (n is an integer from 1 to N) are referred to as intermediate check circuits 120-n-1 to 120-nk. The intermediate check circuit 120-nk (k is an integer of 1 or more and N or less) uses a part of the calculation results in the circuit 110-n as a check range, and checks the occurrence of an error in the check range. The determination circuit 130 obtains check results for a plurality of different check ranges of each of the plurality of circuits 110 from the plurality of intermediate check circuits 120. The determination circuit 130 determines whether there is an error in the circuit 110 based on the obtained check result. The restoration circuit 140 restores the data of the circuit 110 determined by the determination circuit 130 to have an error.

Part or all of the above embodiments may be described as in the following additional notes, but are not limited to the following.

(Additional Note 1) A plurality of intermediate check circuits that set a part of the operation results in each of the plurality of multiplexed circuits as a check range, and check the occurrence of an error in the check range;
determining means for acquiring check results for a plurality of different check ranges of each of the plurality of circuits from the plurality of intermediate check circuits, and determining the presence or absence of an error in the circuit based on the acquired check results;
Restoring means for restoring data of the error generating circuit, which is the circuit determined to have an error by the determining means;
A multiplexing circuit device comprising:

(Additional note 2)
The restoration means includes an error restoration means for restoring configuration data of the error generating circuit.
The multiplexing circuit device according to supplementary note 1.

(Additional Note 3) The error recovery means recovers the configuration data of the error generating circuit using data set in an external memory or by an error correction code.
The multiplexing circuit device according to appendix 2.

(Supplementary note 4) The determining means determines, based on the acquired check results, the error occurrence circuit among the plurality of circuits and the estimated error location that is estimated to include the location where an error has occurred in the error occurrence circuit. Determine,
The multiplexing circuit device further includes partial checking means for checking the estimated error location in the error generation circuit to identify the error occurrence location,
The repairing means is a copying means that performs a copying process of copying the calculation result in the circuit determined to be error-free to the calculation result corresponding to the error occurrence point identified by the partial check means after recovery by the error restoration means. further having,
The multiplexing circuit device according to appendix 2 or appendix 3.

(Supplementary Note 5) The copying means performs the copying process multiple times at the falling edge of the operating clock of the circuit or at a clock that is twice or more the operating clock of the circuit.
The multiplexing circuit device according to appendix 4.

(Additional Note 6) The copying means repeats the copying process until the determining means no longer determines that an error has occurred.
The multiplexing circuit device according to appendix 4 or appendix 5.

(Additional Note 7) The partial checking means performs a cyclical check on the circuit that is determined to be error-free.
The multiplexing circuit device according to any one of appendices 4 to 6.

(Additional Note 8) The partial check means has a partial check circuit corresponding to each of the plurality of circuits,
The partial check circuit corresponding to the error-free circuit performs a cyclic check on the corresponding circuit,
The partial check circuit corresponding to the error occurrence circuit checks the estimated error location in the error occurrence circuit to identify the error occurrence location.
The multiplexing circuit device according to appendix 7.

(Additional Note 9) The plurality of check ranges in the circuit are determined according to any circuit block or stage in the circuit,
The multiplexing circuit device according to any one of Supplementary Notes 1 to 8.

(Supplementary note 10) The intermediate check circuit may check the check range using a cyclic redundancy check of the check range, an error correction code of the check range, or a calculation result of the check range and the check range in another circuit. Performed by comparing with the calculation result of
The multiplexing circuit device according to any one of Supplementary Notes 1 to 9.

(Additional Note 11) Further comprising a majority circuit that outputs the calculation result selected by majority vote from the calculation results of each of the plurality of circuits,
The multiplexing circuit device according to any one of Supplementary Notes 1 to 10.

(Additional Note 12) The plurality of circuits and the majority circuit are implemented in a user circuit,
The multiplexing circuit device according to any one of appendix 11.

(Additional Note 13) The multiplexing circuit device is an FPGA (Field Programmable Gate Array),
The multiplexing circuit device according to any one of Supplementary Notes 1 to 12.

(Additional Note 14) An intermediate check step of setting a part of the calculation results in each of the plurality of multiplexed circuits as a check range, and checking the occurrence of an error in the check range;
a determination step of acquiring check results from the intermediate check step for a plurality of different check ranges of each of the plurality of circuits, and determining whether or not there is an error in the circuit based on the acquired check results;
a repair step of repairing data of the circuit determined to have an error in the determination step;
Error repair method with.

Although the embodiments of the present invention have been described above with reference to the drawings, it is clear that the above embodiments are merely illustrative of the present invention and that the present invention is not limited to the above embodiments. be. Therefore, additions, omissions, substitutions, and other changes to components may be made without departing from the technical spirit and scope of the present invention.

1...FPGA, 2...User circuit, 3-1 to 3-N...Functional circuit, 4-1-1 to 4-N-K...Intermediate check circuit, 5...Majority decision circuit, 6...Error determination circuit, 7-1 ~7-N... Partial check circuit, 8... Soft error countermeasure circuit, 9... Data copy circuit, 10... Memory, 100... Multiplexing circuit device, 110-1 to 110-N... Circuit, 120-1-1 to 120 -N-K...Intermediate check circuit, 130...Judgment circuit, 140...Repair circuit

Claims (8)

a plurality of intermediate check circuits that set a part of the operation results in each of the plurality of multiplexed circuits as a check range and check for occurrence of an error in the check range;
Check results for a plurality of different check ranges of each of a plurality of circuits are acquired from a plurality of intermediate check circuits, and based on the acquired check results , it is determined whether or not there is an error in the circuit, and whether the circuit is determined to have an error. a determination means for determining an estimated error location including a location where an error has occurred in an error generation circuit that is a circuit ;
partial checking means for checking the estimated error location in the error occurrence circuit to identify the error occurrence location;
Restoration means for restoring data in the error generating circuit;
Equipped with
The repair means includes:
error recovery means for recovering configuration data of the error generating circuit;
and a copying means that performs a copy process of copying the calculation result in the circuit determined to be error-free to the calculation result corresponding to the error occurrence location identified by the partial check means, after recovery by the error recovery means.
Multiplexing circuit device. The copying means performs the copying process a plurality of times at the falling edge of the operating clock of the circuit or at a clock that is twice or more the operating clock of the circuit.
The multiplexing circuit device according to claim 1 . The copying means repeats the copying process until the determining means no longer determines that there is an error.
A multiplexing circuit device according to claim 1 or claim 2 . The partial checking means cycles through the entire circuit that has been determined to be error-free and performs an error check.
The multiplexing circuit device according to any one of claims 1 to 3 . The partial check means has a partial check circuit corresponding to each of the plurality of circuits,
The partial check circuit corresponding to the error-free circuit cycles through the entire corresponding circuit to check for errors;
The partial check circuit corresponding to the error occurrence circuit checks the estimated error location in the error occurrence circuit to identify the error occurrence location.
The multiplexing circuit device according to claim 4 . The plurality of check ranges in the circuit are determined according to any circuit block or stage in the circuit,
A multiplexing circuit device according to any one of claims 1 to 5 . The intermediate check circuit checks the check range using a cyclic redundancy check of the check range, an error correction code of the check range, or a calculation result of the check range and a calculation result of the check range in another circuit. This is done by comparing
A multiplexing circuit device according to any one of claims 1 to 6 . An error recovery method performed by a multiplexing circuit device, the method comprising:
an intermediate check step of setting a part of the calculation results in each of the plurality of multiplexed circuits as a check range, and checking the occurrence of an error in the check range;
Obtain check results from the intermediate check step for a plurality of different check ranges of each of the plurality of circuits, and determine whether or not there is an error in the circuit based on the obtained check results , and in the circuit determined to have an error. a determination step of determining an estimated error location that is estimated to include a location where an error has occurred in a certain error occurrence circuit ;
a partial check step of checking the estimated error location in the error occurrence circuit to identify the error occurrence location;
an error recovery step of recovering configuration data of the error generating circuit;
a copying step of performing a copy process of copying the calculation result in the circuit determined to be error-free to the calculation result corresponding to the error occurrence location identified in the partial check step after recovery by the error recovery step;
Error repair method with.

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