JPS5880745A - Diagnosing system - Google Patents

Abstract

PURPOSE:To reduce the quantity of hardware of an auxiliary diagnosing circuit without lowering the diagnosing performance, by enabling the diagnosis of a logical circuit containing an FF which is incapable of scan-in/scan-out. CONSTITUTION:Test data is scanned into an FF10 which is capable of scan-in/ scan-out. Then a system clock Cj is supplied to an FF12 which is incapable of scan-in/scan-out, and the output state of a combined circuit 11 is fetched to the FF12. A system clock Ci is supplied to an FF14 which is capable of scan-in/ scan-out, and the output state of a combined circuit 13 is fetched to the FF14. Finally the FF14 is scanned out. The scan-out data delivered to a scan-out data SOD line 5 is compared with the expected value obtained previously. Then the normal or abnormal state is decided for a logical circuit including the circuits 11 and 13 and the FF12. If the logical circuit is abnormal, the abnormal state is decided. This operation enables the diagnosis even for an FF which is incapable of scan-in/scan-out.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a diagnostic technique #I in a logic device, and particularly to a diagnostic method that can reduce the amount of hardware required for a diagnostic auxiliary circuit.

In the conventional logic device diagnosis method, the combinations to be diagnosed are
Each flip-flop (F'
I (abbreviated as ")" can be scanned in and scanned out from the scan control circuit.

Then, test data is scanned in to the input 1 rule 1i"F' [, 2 to set the input state of the combinational circuit in the diagnostic pair. Then, the output side I, 1) and the clock are input to N 11 (
1-7, the output state of the combination rrll path in the diagnostic pair is set to the output side 1. After adding weight to N 1,1, output 411
11 Scan out FIi'. This scanout data is used for the tth time, and by comparing it with the data, the circuit that matches the output of the diagnostic pair is diagnosed.

In this way, in the past, there was no way of inputting or outputting the diagnostic result into the output circuit.
I had to scan in and scan out the F. The combinational circuits before and after the FF, which cannot be scanned out, were excluded from the diagnosis ZII41.

However, recent logic devices such as large electronic computers,
It contains an extremely large number of FFs, and in order to achieve a high detection rate with conventional diagnostic methods, it is necessary to be able to scan in and scan out a huge number of FFs.

This results in an increase in the amount of hardware for the diagnostic auxiliary circuit, including a scan control circuit for controlling scan-in/scan-out of the FFs, and associated circuits, resulting in an increase in cost.

SUMMARY OF THE INVENTION It is, therefore, an object of the present invention to provide a diagnostic method that reduces the amount of hardware in a diagnostic auxiliary circuit and achieves a high detection rate.

Therefore, in the diagnostic method according to the present invention, between the first and second 1"F where scan-in and scan-out are possible, one or more third
1-' For a logic circuit formed by connecting two or more combinational circuits in series with an F interposed, test data is scanned into the first FF on the input side of the logic circuit, and then supplying a clock to each of the third F''FKs in order from the one closest to the first OFF', and then supplying a clock to the second OFFK, and then scanning out the second OFF; The logic circuit is diagnosed based on this scanout data.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, 1(j, +4 is 1F which allows scan-in and scan-out, and 11F where neither 12-bit scan-in nor 7-bit scan-out is possible).

11 and 13 are circuits in which the output of the FF of the first bite is manually powered.

In the conventional diagnosis 1 @ Manshiki, Soshi Senaka 1 circuits that exist before and after FF 12, which cannot be scanned in/scanned out, like combinational circuits 11 and 13, are excluded from the diagnosis. In the present invention, these diagnoses can be performed as detailed below.

The scanout of F'#'l(,,14 is II'F
” 10 t or 14 addresses to address decoder 4
The scan-out data is output to the SOD line 5 through the 01 gate A and selectively enabling the scan-out gate 24 or 27 with the output of the address decoder 4. .

(3) Scan-in is performed by inputting an address specifying FF1G or FF14 to the address decoder 4, setting the SID line l to the scan-in state, and then supplying a trigger signal to the SIT line 2. It will be done. For example l
i” F 10 (specify 14, set SID line l to °°l”
When set to , F F 10 (14) is set at the output of ANI) 22 (25). F F'
10 (14) is reset by specifying the address of the FF and supplying the SIR line 3 with the signal “I II”.
F F' 10f14) is reset by the output of the D gate 23@.

The scan-in/scan-out operations and the circuits therefor are the same as those of the prior art, and therefore will not be described further.

In the present invention, by utilizing the scan-in/scan-out function described in L, the combinational circuit 11. which could not be diagnosed conventionally.
In order to enable the diagnosis of FF13, the clock line 21 that supplies the system clock Cj to the FF12 and the FF10.1
4 and the clock line supply for supplying the system clock C1 are made independent.

Figure 2 shows the clock lines 20 and 21 supplying clocks
4) This is an example of a circuit. ; 30 is a microinstruction register in which microinstructions are set. The microinstruction decoder 31 decodes the instruction field of the microinstruction register (M) and activates the timing control 111 times 1'832. Upon receiving this activation, the timing control circuit 32
is the phase relationship according to the contents of the phase mask field of the microinstruction register 30, and the system clocks C, .
Cj and other system clocks.

During normal plowing (other than during diagnosis), for example, see Figure 3 (a).
The system clock C11Cj is outputted from the timing control circuit 32 with the phase relationship shown in FIG.

On the other hand, during diagnosis, the system clock C1XCj is outputted with the phase relationship shown in FIG. 3(b), for example.

This is possible by first setting a microinstruction for sending out the system clock Cj in the microinstruction register (i), and then setting a microinstruction for sending out the system clock Ci.

Next, the diagnostic operation will be explained.

First, test data is scanned into the FF 10 using the method described above. Next, set the system clock Cj to F
F'12 and output state of combinational circuit 1]
12 Take in K. Next, the system clock C1 is supplied to the P F 14, and the output state of the combinational circuit 13 is F.
Import it into F I”14.Finally, import it into F I”1 using the method described above.
Scan out 4. The scanout data output to the 5ODi 5 is compared with the expected value determined in advance, and the scanout data is outputted to the combinational (b) paths 11, 13 and F'F' 12.
It is determined whether the logic circuit including the logic circuit is normal or not, and if it is still abnormal, its status is determined. The means for making a determination based on such scanout Φ data may be the same as the conventional method, so the details will be omitted.

This embodiment uses an FF that can scan in/scan out.
This is an example in which only one PF, which cannot be scanned in/scanned out, is present in a circuit narrowed down to a narrow circuit. If two or more scan-in/scan-out impossible F
If F is interposed, after scanning the test data to the input side F'F, supply a clock to each intervening FP from the one closest to the input side to ++m, and then supply and scan the clock to the output side F. Just execute out.

Further, in this embodiment, the clock sending instruction is controlled by microinstructions, but it may be replaced by another manual control processor, for example, a control processor dedicated to diagnosis.

Furthermore, it is clear that the present invention can also be applied to module (package, LSI) testing if the entire diagnostic execution control in the present invention is performed by a control processor (for example, a package tester) dedicated to diagnosis.

As described above, according to the present invention, it becomes impossible to diagnose even the logical path 1l-f' in which 1, 1, and 1, which cannot be scanned in or scanned out. In other words, it allows scan-in/scan-out)
Even if the number of degrees Fahrenheit is reduced compared to the conventional method, the detection rate of t can be achieved at the same rate as the conventional method. Therefore, it is possible to reduce the hardware B of diagnostic aid 1 + jl without reducing the diagnostic performance and 4t, or to significantly improve the diagnostic performance by keeping the hardware of the diagnostic aid circuit to the same level as in the past. can be directed.

[Brief explanation of the drawing]

+tr No. 2 shows an embodiment of the present invention.
The figure is a block diagram showing an example of a circuit for controlling transmission of the system clock, and FIG. 3 is a block diagram showing the timing of the system clock. 1.2.3... Signal lines related to scan-in/scan-out, 4... Atto/scan decoder, 5...
・Scanout data output line,], 1, 1...
・Flip float y'(1'F"), 12...scan-in/scan-out possible
non-scannable flip-flop (PP),
11゜i3...Combination circuit, 20.21...System clock supply line, 22-2'7...A, N L
) gate, 2J3...o R gate.

Claims (1)

[Claims] ■ ↑…(
Then, for one logic circuit consisting of 12 or more combinational circuits connected in a 4-way manner with one or more third FF intervening, which is inconvenient for both scan-in and scan-out, the cough logic circuit is Fill If: Scan in the test data to the first 1'F located, then supply the clock to the third 1'F from the one closest to the FF of the core 11m. 2. Next, after supplying a clock to the second J+IJ+1 of Plan P, the second F"l(' is scanned out, and based on this scanout data, the 1st route is diagnosed. Diagnostic method.