JPS5879334A - Logical circuit - Google Patents

Logical circuit

Info

Publication number
JPS5879334A
JPS5879334A JP56178037A JP17803781A JPS5879334A JP S5879334 A JPS5879334 A JP S5879334A JP 56178037 A JP56178037 A JP 56178037A JP 17803781 A JP17803781 A JP 17803781A JP S5879334 A JPS5879334 A JP S5879334A
Authority
JP
Japan
Prior art keywords
transistor
current
circuit
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56178037A
Other languages
Japanese (ja)
Other versions
JPH0338776B2 (en
Inventor
Mitsutoshi Sugawara
光俊 菅原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56178037A priority Critical patent/JPS5879334A/en
Publication of JPS5879334A publication Critical patent/JPS5879334A/en
Publication of JPH0338776B2 publication Critical patent/JPH0338776B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/001Arrangements for reducing power consumption in bipolar transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce the power consumption, by providing a current mirror circuit inputting an emitter current of an input transistor (TR) for a TR logical circuit. CONSTITUTION:A diode 11 and a TR3' constitute a current mirror circuit inputting the emiter current of an input TR2, one output is obtained from its output terminal 8' and a TR4 is connected to a collector of the input TR via a level shift diode 12 and another output is obtained from its collector. A signal at an input terminal 1 is inverted at the TR2, and an output further inverted at the TRs 3', 4 is generated at outputs 8' and 9. Since a current multiplied by the current amplification factor of the current mirror circuit for the emitter current flows to the TR3' when the TR2 is set on, the TR3' can sufficiently by driven.

Description

【発明の詳細な説明】 本発明はトランジスタ論理回路に関し、特に低電力で動
作させる集積回路において有効なトランジスタ論理回路
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to transistor logic circuits, and more particularly to transistor logic circuits useful in integrated circuits operated at low power.

第1図は従来のトランジスタ論理回路の一例で、いわゆ
るRTL(Resistor TransistLrL
ogic)と呼ばれ−ているものを示す回路接続図であ
る。lは入力端子s 2,3.4はトランジスタ、5.
6.7は抵抗、8,9は出力端子、10は電源である。
FIG. 1 shows an example of a conventional transistor logic circuit, so-called RTL (Resistor TransistLrL).
FIG. 1 is an input terminal s2, 3.4 is a transistor, 5.
6.7 is a resistor, 8 and 9 are output terminals, and 10 is a power supply.

端子1よシ入カされた信号はトランジスタ2で反転され
、そのコレクタから抵抗6.7を介してそれぞれトラン
ジスタ3.4のペースに入力される。トランジスタ3お
よび4にょシさらに反転されそれぞれ端子8,9よシ出
カがとシだされる。抵抗5#i負荷であJ)%10は電
源である。
The signal inputted from terminal 1 is inverted by transistor 2, and inputted from its collector to the respective paces of transistors 3.4 via resistor 6.7. Transistors 3 and 4 are further inverted and outputs are output from terminals 8 and 9, respectively. Resistor 5#i load and J)%10 is the power supply.

上記回路を集積回路内に作る場合を考えると、票子占有
面積の点から抵抗5の値としては50にΩ程度が実用上
の上限である。を次消費電力の点からは抵抗5は大きい
ほうが好ましいので、50にΩとすることを考える。一
段あたシの消費電力は抵抗5における消費電力とほぼひ
としく、となる、第1図のような回路をたくさん用いる
場合には消費電力は大きくなってしまう、たとえば10
0ケ用いるとすると288mWとなってしまう。
Considering the case where the above circuit is formed in an integrated circuit, the practical upper limit for the value of the resistor 5 is about 50Ω from the viewpoint of the area occupied by the circuit board. From the point of view of power consumption, it is preferable for the resistor 5 to be large, so consider setting it to 50Ω. The power consumption of one stage is almost the same as the power consumption of the resistor 5, and if a large number of circuits as shown in Fig. 1 are used, the power consumption will increase, for example, 10
If 0 is used, the power will be 288 mW.

この値は集積回路のパッケージで決まる最大許容損失に
近い値であシ、他に多くの回路を集積できないことを意
味する。
This value is close to the maximum allowable dissipation determined by the integrated circuit package, and means that many other circuits cannot be integrated.

本発明は、回路構成が簡単で消費電力の極めて少ない論
理回路を提供することを目的とする。
An object of the present invention is to provide a logic circuit with a simple circuit configuration and extremely low power consumption.

本発明咳よれば、入力トランジスタ及び該入ヵトランシ
スタのエミッタ電流を入力とするカレントミラー回路と
を少なくとも備え、前記入力トラことを特徴とする論理
回路が得られる。
According to the present invention, there is obtained a logic circuit characterized by comprising at least an input transistor and a current mirror circuit whose input is the emitter current of the input transistor, and characterized by the input transistor.

次に実施例に従い図面を用いて本発明の詳細な説明する
Next, the present invention will be described in detail according to embodiments using drawings.

第2図は本発明の一実施例を示す回路接続図で、1は入
力端子、2.3’、4はトランジスタ、5′は定電流源
%8’−9は出力端子、10は電源である。ダイオード
11とトランジスタ3′で入力トランジスタ2のエミッ
タ電流を入力とするカレントミラー回路t−構成してい
る。ダイオード12はレベルシフト用ダイオードである
Fig. 2 is a circuit connection diagram showing an embodiment of the present invention, where 1 is an input terminal, 2.3', 4 are transistors, 5' is a constant current source, 8'-9 is an output terminal, and 10 is a power supply. be. The diode 11 and the transistor 3' constitute a current mirror circuit t- which receives the emitter current of the input transistor 2 as an input. Diode 12 is a level shift diode.

第1図において抵抗5を小電流の定電流回路におきかえ
れば、消費電力を小さくすることは可能であるが、抵抗
6,7に生ずる電圧降下も小さくなって、トランジスタ
3.4の電流ホッギング現象が生じてしまい、トランジ
スタ3,4のコレクタ電流がバランスよく流れなくなる
。このため抵抗6.71に大きくし所定の電圧降下をも
たせる必要があシ、したがって抵抗6,7の素子占有面
積の増大をまねき実用的でない0本発明においては、こ
の問題を避けるため、カレントはラー回路の出力端子8
′から一方の出力を得るようにしである。
In Fig. 1, if the resistor 5 is replaced with a constant current circuit with a small current, it is possible to reduce power consumption, but the voltage drop that occurs across the resistors 6 and 7 is also reduced, and the current hogging of the transistor 3.4 is reduced. This phenomenon occurs, and the collector currents of transistors 3 and 4 no longer flow in a balanced manner. For this reason, it is necessary to make the resistor 6.71 large to provide a predetermined voltage drop, which results in an increase in the area occupied by the resistors 6 and 7, making it impractical.In the present invention, in order to avoid this problem, the current error circuit output terminal 8
′ to obtain one output.

すなわち、トランジスタ2のコレクタには、レベルシフ
ト用ダイオード12t−介してトランジスタ4のみがつ
くので電流ホッギングは生じないのみでなく、トランジ
スタlが導通時にその工2.り電流をカレントミラーの
電流増幅変倍した電流がトランジスタ3’ l!れうる
ので、トランジスタ3′を十分に駆動できることになる
That is, since only the transistor 4 is connected to the collector of the transistor 2 via the level shift diode 12t, not only does current hogging not occur, but also when the transistor 1 is conductive, the current hogging occurs. The current obtained by amplifying and scaling the current of the current mirror is transmitted to the transistor 3'l! Therefore, the transistor 3' can be sufficiently driven.

出力端子8’ 、 9Fx、例えば定電流源(図示せず
)によって、高電位にプルアップされているものとする
。この場合、トランジスタ3’ 、 417)導通時の
コレクタ電流は、前記定電流源の電流をすヘテすいこみ
うる駆動能力をもつようにトランジスタ3′、4のエミ
ッタ面積を設定しておく。(通常1:l〜1:3程度で
よい)入力端子に加わる入力カ″′Hルベルすなわちト
ランジスタ20ベース・エイ、゛夕闇の順方向電圧Vl
lとダイオード11の順方向電圧VF (=VB B 
) (D和(Vn m +VF )よシ大きいときは、
トランジスタ2,3′が導通し、端子8′にはトランジ
スタ3′のコレクタ・エイ、り関節和電圧VCI(sa
t)に等しい低電位出力が得られ、端子9には高電位に
ほぼ等しい1H”レベル出力が得られ、入力が(VBl
+VF)未満のl 1.1″レベルのときには、端子8
′に高電位(”H”レベル)、端子9に低電位(′″L
”レベル)出力が得られ名。
It is assumed that the output terminals 8' and 9Fx are pulled up to a high potential by, for example, a constant current source (not shown). In this case, the emitter areas of the transistors 3' and 417 are set so that the collector current when the transistors 3' and 417 are conductive has a driving ability that can fully absorb the current of the constant current source. (usually about 1:l to 1:3) The input voltage applied to the input terminal is the transistor 20 base ei, the forward voltage Vl of the dusk.
Forward voltage VF (=VB B
) (When D is larger than (Vn m +VF),
Transistors 2 and 3' are conductive, and terminal 8' has a collector voltage VCI (sa) of transistor 3'.
A low potential output equal to t) is obtained, a 1H" level output approximately equal to the high potential is obtained at terminal 9, and the input is
+VF) When the level is less than 1.1", terminal 8
' high potential ("H" level), low potential ('"L level) at terminal 9.
” level) output is obtained.

定1流源を複数個設けることは、!ルチコレクタPNP
)ランジスタを用いて実現できるので、従来と同程度の
消費電力で比較し次場合、素子占有面積は著しく小さく
できるし、定電流源の値は理論上非常に小さくできるの
で、占有面積の小さな低消費電力の論理回路が実現され
る。実際上、定電流源の値を各々1oJIAK設定する
ことができ、その場合の一段当カの消費電力はほぼ 12(V)X10−’(A)X3=0.00036(W
)とな〕従来の1/8に低減され、占有面積も同等以下
とすることができる。ここで3倍したのは第2図の回路
で論理回路1段に相当すると考えられるからである。但
し、後に示すように、特殊な場合には%3倍する必要は
ない。
Providing multiple constant flow sources is! Multi-collector PNP
) Since it can be realized using a transistor, the area occupied by the element can be significantly reduced compared to the conventional one with the same power consumption, and the value of the constant current source can theoretically be made very small. A power consumption logic circuit is realized. In practice, the value of each constant current source can be set to 1oJIAK, and in that case, the power consumption of one stage is approximately 12 (V) x 10 -' (A)
)] is reduced to 1/8 of the conventional one, and the occupied area can be reduced to the same level or less. The reason for multiplying by three here is that the circuit shown in FIG. 2 is considered to correspond to one stage of logic circuit. However, as shown later, in special cases there is no need to multiply by %3.

第3図は従来のRTL形式のR−871ツブフロツプの
一例を示す回路接続図である。31FiR入力、32は
S入力、33はQ出力であシ、34〜38はトランジス
タ、39〜43は抵抗、44は電源である。説明のつご
う上まず端子31が@H”レベル、端子32が@L”レ
ベルのときを考えると隻 トランジスタ34がON(導
通)シ、そのコレクタ電位はII L 11に−tzb
、トランジスタ36が0FF(遮断)し、tたトランジ
スタ37もOFFのため、トランジスタ36.37のコ
レクタ電位が′HIlになシトランジスタ35と38が
ONする。次に端子30−L”にしても、前述のように
トランジスタ35がONI、て匹るため、他の状NI4
は変化しない。次に端子32t−”H”にすると、トラ
ンジスタ37がONし、そのコレクタ電位は@L”にな
シ、トランジスタ35と38がOFFになシ、ま友トラ
ンジスタ34もOFFのためトランジスタ34,35の
コレクタは1H”とな)、トランジスタ36がONする
0次に端子32t@L”にしても、前述のようにトラン
ジスタ36がONしている友め、他の状態は変化しない
0以上でR−Sフリップフロップの動作が説明された。
FIG. 3 is a circuit connection diagram showing an example of a conventional RTL type R-871 block flop. 31 is a FiR input, 32 is an S input, 33 is a Q output, 34 to 38 are transistors, 39 to 43 are resistors, and 44 is a power supply. For the sake of explanation, first consider when the terminal 31 is at @H" level and the terminal 32 is at @L" level. When the transistor 34 is ON (conducting), its collector potential becomes II L11 -tzb.
Since the transistor 36 is turned off (cut off) and the transistor 37 is also turned off, the collector potentials of the transistors 36 and 37 become 'HIl', and the transistors 35 and 38 are turned on. Next, even if the terminal 30-L" is set, the transistor 35 remains ONI as described above, so the other state NI4
does not change. Next, when the terminal 32t is set to "H", the transistor 37 is turned on, its collector potential is @L", the transistors 35 and 38 are turned off, and the Mayu transistor 34 is also turned off, so the transistors 34, 35 are turned off. Even if the transistor 36 is turned ON and the terminal 32t@L'' is set to 0, the transistor 36 is turned ON as described above, and the other states do not change. - The operation of the S flip-flop was explained.

この回路は第1図と同様に低電力化するのはむずかしい
Similar to the circuit shown in FIG. 1, it is difficult to reduce the power consumption of this circuit.

第4図は本発明の他の実施例である省電力化したR−8
フリツプ70ツブの回路接続図である。
Figure 4 shows a power-saving R-8 which is another embodiment of the present invention.
It is a circuit connection diagram of flip 70 tube.

第3図と同一のものには同一の番号を付しである。Components that are the same as in FIG. 3 are given the same numbers.

第3図の負荷抵抗39.42のかわりに本発明ではトラ
ンジスタ47による定電流源を用いている。
In place of the load resistors 39 and 42 in FIG. 3, the present invention uses a constant current source formed by a transistor 47.

また、第3図では、トランジスタ36,370コレクタ
にはトランジスタ35と38が接続されてbるので、電
流ホギング防止のために抵抗41゜43が必要だっ友が
、本発明ではトランジスタ38のベースの接続点を変更
することにょ)上記抵抗を不必要にし友、トランジスタ
38に流す電流はトランジスタ36.37のコレクタ電
流中エミッタ電流と相反関係にある必要があるため、反
転出力のトランジスタ34.35の工建、タ電流全ダイ
オード45とトランジスタ38からなるカレントミラー
回路を用いて作っている。なお、ダイオード46はレベ
ルシフト用である。
In addition, in FIG. 3, since transistors 35 and 38 are connected to the collectors of transistors 36 and 370, resistors 41 and 43 are required to prevent current hogging, but in the present invention, the base of transistor 38 is By changing the connection point, the above-mentioned resistor can be made unnecessary.Since the current flowing through the transistor 38 needs to have a reciprocal relationship with the collector current and the emitter current of the transistors 36 and 37, the transistors 34 and 35 with the inverted output It is made using a current mirror circuit consisting of a diode 45 and a transistor 38. Note that the diode 46 is for level shifting.

端子31が@H″レベル、端子32が@ L @レベル
のときは、トランジスタ34がONし、そのコレクタ電
位は”L”とな夛、トランジスタ36がOFF l、、
またトランジスタ37もOFFのため、トランジスタ3
6.37のコレクタ電位が1H”とな〕、トランジスタ
35がONする。トランジスタ38はトランジスタ34
がONになることによってONとなる0次に端子31を
@ L @にしても、トランジスタ35がONになって
いるため、他の状標の変化はない。次に端子32に′H
″にスルト、トランジスタ37がONし、そのコレクタ
電位は′″L”になり、トランジスタ35がOFFにな
夛、トランジスタ34もOFFしているため、トランジ
スタ38となシ、同時にトランジスタ36もONとなる
。次に端子321″@L′″にしてもトランジスタ36
がONしているため他の状態は変化しない。
When the terminal 31 is at @H'' level and the terminal 32 is at @L level, the transistor 34 is turned on, its collector potential is “L”, and the transistor 36 is turned off.
In addition, since transistor 37 is also OFF, transistor 3
When the collector potential of 6.37 becomes 1H'', the transistor 35 turns on.
Even if the 0th order terminal 31, which is turned on by turning on, is set to @L, there is no change in other conditions because the transistor 35 is turned on. Next, connect terminal 32 to 'H.
'', transistor 37 is turned on, its collector potential becomes ''L'', transistor 35 is turned off, and transistor 34 is also turned off, so transistor 38 and transistor 36 are turned on at the same time. Next, even if we set the terminal 321″@L′″, the transistor 36
Since is ON, other states do not change.

このR−8713ツブプロツプでは、電源回路48以外
には抵抗を必要としないため、R−8フリツプフロ、プ
段の消費電力はトランジスタ47のコレクタ電流の設定
次第では本質的にいくらでも小さくできる。九とえばこ
の電流t−10μAに設定することによシ従来の1/2
0以下にすることが可能である。電源回路48の内部は
電源44から抵抗52t′介してダイオード53に約α
7vの電圧を発生させ、トランジスタ50と抵抗51か
らなる回路で、定電流を発生させ、これをダイオード4
9とトランジスタ47からなるチレントミラー回路で所
望の電流源を作っている。ここで友とえば抵抗52t2
2.6にΩ、抵抗511−4.2にΩとすることによシ
、トランジスタ47の各コレクタ電流t−10−ムに設
定で勇る。これらの抵抗値は集積回路に適した値である
。電源回路4Bからはトランジスタ47に供給するばか
〕でなく、他の論理回路へも供給することが可能である
Since this R-8713 block prop requires no resistance other than the power supply circuit 48, the power consumption of the R-8 flip-flop stage can essentially be made as small as desired depending on the setting of the collector current of the transistor 47. 9. For example, by setting this current to t-10 μA, the current can be reduced to 1/2 of the conventional value.
It is possible to make it 0 or less. Inside the power supply circuit 48, approximately α is connected to the diode 53 from the power supply 44 through the resistor 52t'.
A voltage of 7V is generated, a constant current is generated by a circuit consisting of a transistor 50 and a resistor 51, and this is connected to a diode 4.
A desired current source is created by a tilent mirror circuit consisting of a transistor 9 and a transistor 47. Here, for example, resistor 52t2
By setting Ω to 2.6 and Ω to resistor 511-4.2, each collector current of transistor 47 can be set to t-10-m. These resistance values are suitable for integrated circuits. It is possible to supply power from the power supply circuit 4B not only to the transistor 47 but also to other logic circuits.

以上のように本発明によれば本質的にはいくらでも省電
力化可能表トランジスタ論理回路が構成でき、工業上き
わめて有用である。
As described above, according to the present invention, essentially any number of power-saving table transistor logic circuits can be constructed, and the present invention is extremely useful industrially.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のRTL回路の一例、第2図は本発明の実
施例、第3図は従来のR8フリップフロップの一例、第
4図は本発明を実施したR8フリップフロップの一例を
それぞれ示す回路接続図である。 1.31.32・・・・・・入力端子、2,3.3’ 
。 4.34,35,36,37,38,47.50・・・
・・・トランジスタ、5,6,7,39,40,41゜
42.43,51.52・・・・・・抵′抗″% 5′
・・・・・・定電流源、8.8’ 、9,33.33’
・・・・・・出力端子、10.44・・・・・・電源%
 11,12,45,46゜49.53・・・・・・ダ
イオード、48・・・・・・電源回路。
FIG. 1 shows an example of a conventional RTL circuit, FIG. 2 shows an embodiment of the present invention, FIG. 3 shows an example of a conventional R8 flip-flop, and FIG. 4 shows an example of an R8 flip-flop implementing the present invention. It is a circuit connection diagram. 1.31.32...Input terminal, 2,3.3'
. 4.34, 35, 36, 37, 38, 47.50...
...Transistor, 5,6,7,39,40,41゜42.43,51.52...Resistance'% 5'
... Constant current source, 8.8', 9,33.33'
...Output terminal, 10.44...Power supply%
11, 12, 45, 46° 49.53... Diode, 48... Power supply circuit.

Claims (1)

【特許請求の範囲】[Claims] 入力トランジスタと、該入力トランジスタのユミッタ電
流を入力とするカレントミラー回路と、前記入力トラン
ジスタのコレクタ及び前記カレントきラー回路の出力の
少なくとも一方から論理出力を得る手段とを備えてなる
ことt−特徴とする論理回路。
Features: an input transistor; a current mirror circuit that receives a transmitter current of the input transistor; and means for obtaining a logic output from at least one of the collector of the input transistor and the output of the current filter circuit. A logic circuit that
JP56178037A 1981-11-06 1981-11-06 Logical circuit Granted JPS5879334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56178037A JPS5879334A (en) 1981-11-06 1981-11-06 Logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56178037A JPS5879334A (en) 1981-11-06 1981-11-06 Logical circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP1065150A Division JPH0220914A (en) 1989-03-17 1989-03-17 Logic circuit

Publications (2)

Publication Number Publication Date
JPS5879334A true JPS5879334A (en) 1983-05-13
JPH0338776B2 JPH0338776B2 (en) 1991-06-11

Family

ID=16041477

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56178037A Granted JPS5879334A (en) 1981-11-06 1981-11-06 Logical circuit

Country Status (1)

Country Link
JP (1) JPS5879334A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5061975A (en) * 1973-09-29 1975-05-27
JPS56115036A (en) * 1980-02-16 1981-09-10 Sony Corp Interface circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5061975A (en) * 1973-09-29 1975-05-27
JPS56115036A (en) * 1980-02-16 1981-09-10 Sony Corp Interface circuit

Also Published As

Publication number Publication date
JPH0338776B2 (en) 1991-06-11

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