JPS587868A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the size of a semiconductor device and to eliminate diffusion capacity of the device by epitaxially growing a single crystal Si thicker than the thickness of a dielectric on an amorphous dielectric formed partly on a substrate, and forming an insulated gate FET with the Si as a base. CONSTITUTION:An oxidized film 32 is fored on a substrate 31 and is patterned. Si is epitaxially grown on the film, and a smooth P type single crystal Si film 33 is accumulated on the Si. A gate oxidized film 34 is formed, an impurity 35 is injected, and a gate electrode 35 is then formed. Arsenic ions are implanted, thereby forming source and drain region 37. An interlayer insulating film 38 is accumulated. In this manner, the size of the element is shortened, and diffusion capacity is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor device 41KI! The present invention relates to an L-edge gate type transistor and a method of manufacturing a semiconductor integrated circuit including the same at least in part.

Conventionally, a general insulated gate field effect transistor has an isolation region and an active region provided in a plane on the surface of a silicon single crystal substrate. were formed respectively. However, in this conventional structure, since there is a PN junction capacitance between the drain diffusion region and the substrate, the switching speed t of the transistor is limited by the size of the capacitance unless the total capacitance disappears. This has been a hindrance to increasing the speed of devices. For this reason, one way to increase speed by reducing the junction capacitance between the substrate and the drain is to use 5O8 (5ilicon on
It has been proposed for some time to dielectrically separate the substrate and drain connections by using a t This has become a practical problem due to the tendency for junction leakage to occur. Single crystal silicon is deposited on the surface and polycrystal silicon is deposited on the dielectric surface.
The structure of a semiconductor device in which the source and drain of an MO8 field effect transistor are formed of polycrystalline silicon on a dielectric material is R.
OMOS (Buried Qxld* MD S)
As I.E.E.Transaccene OnElectronic Devices ED-23 No.10, 10
Page 00 (I EEE Transaetrons
on El@ctron Device@sμ ED-231190 (1976) KjII! proposed 0
It is difficult to use it in this channel region, and in many cases it is not possible to use it in element design, such as considering the O transition section between the single crystal and the polycrystal, making it difficult to apply miniaturization technology.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-mentioned conventional drawbacks.

According to this IA, in the process of partially providing an amorphous dielectric material on a single crystal silicon substrate, the type and amount of impurities are added so that the film thickness of the amorphous dielectric material is at least as thick as that of the amorphous dielectric material. a step of depositing at least one layer of epitaxial silicon in a controlled manner; a step of forming a gate insulating film; and a step of providing at least a region to be a north drain in a single crystal silicon substrate on the amorphous dielectric. A method for manufacturing a semiconductor device is obtained that includes **.

Hereinafter, the conventional ROMOS configuration and the configuration of the present invention will be compared and explained in detail with reference to the drawings. Figure 1 #'iBOMOSS
FIG. 2 is a schematic cross-sectional view showing the simple manufacturing process MK in order to describe the 41 image of the structure. It is a typical sectional view shown in comparison with JK.

Usually 1 and 21 are silicon substrates, 2 and 22 are silicon oxide films, 3 and 23 are epitaxial silicon,
4 polycrystalline silicon deposited during epitaxial growth; 24 monocrystalline silicon layer deposited on silicon oxide amorphous dielectric; 5 field oxide; 6 and 26 gate oxidizer; 7 and 27 is polycrystalline silicon for gate electrode, 8 and 28 are source/drain regions,
9 and 29 are interlayer insulating films, such as PSG, 1G, and aO #i aluminum wiring electrodes. This feature makes it possible to significantly reduce the diffusion capacitance on the drain side, where voltage is applied in most cases, and is expected to provide high-speed operation. However, since the silicon on the dielectric is polycrystalline and is deposited on the entire surface of the dielectric, the mobility of holes in electrons in polycrystalline silicon is extremely low, making it difficult to use it in the channel region or a part of it. It is difficult to remove unnecessary polycrystalline silicon or transform it into an insulating film using the LOCO8 method in order to separate the substrate of the two transistors, which inevitably increases the element size. If any of these steps becomes a membership fee and the number of masks increases, it has a disadvantage. On the other hand, in Figure 92, the stile,
Since monocrystalline silicon is deposited on the dielectric 22, the channel region 4L< can be formed as a part thereof. In this way, the interval separated by the dielectric can be reduced and the source/drain regions can be formed on the dielectric film, making it possible to shorten the device dimensions and greatly reduce the diffusion capacitance.

Furthermore, a major feature of the present invention is that the dielectric film thickness
By depositing epitaxial silicon, monocrystalline silicon is formed at a certain distance from the edge of the dielectric, and is not deposited on the dielectric surface further away. This distance depends on the difference between the epitaxial crystalline film thickness and the dielectric film thickness and the orientation of the substrate used. Therefore, by setting the substrate orientation, epitaxial silicon film thickness, and dielectric width dimension, a selective epitaxial silicon substrate can be deposited at any location in the island shape shown in Figure 2 without the need for a mask fitting process. 0 Such selective epitaxial growth is mainly performed using dichlorosilane <81% C11) and a gas containing chlorine atoms, and the volume of chloride water produced contributes to etching of silicon. In particular, this is thought to be a result of the etching rate being lower than the deposition rate for silicon 1.O also, for silicon 9, epitaxial silicon, which is thicker than the dielectric film thickness, grows on the surface near the edge of the dielectric, and the epitaxial silicon grows laterally from the edge of the dielectric. Thus, by using the present invention, epitaxial silicon can be separated into islands in a self-aligned manner so as to include an amorphous dielectric surface W. As a result, the drain diffusion capacitance tube can be significantly reduced and the device speed can be increased.
Furthermore, there is a great advantage that the fabrication process can be simplified and the element dimensions can be shortened without increasing the number of alignment mask steps.

Next, the present invention will be explained in detail using Example twJ. Figure 3 is a rounded diagram for explaining the manufacturing process of β, an insulating cat-lid field effect transistor to put the present invention into practice, and shows a cross section of the element in the cage process.
A silicon substrate 31 with a <100> orientation is formed with a film 32 of about 500 kHz by thermal oxidation, and then patterned into a desired shape by ordinary photolithography and etching. Add gas dichlorosilane (St) 12C1,) source gas and hydrogen chloride gas, and boil under reduced pressure of about 80°C to 108°C.
When silicon is epitaxially grown to a film thickness of about 500.degree. C. at a substrate temperature of 0.degree. C., a smooth monocrystalline silicon film of Pffi is deposited on a portion of the surface of the silicon substrate and the surface of the oxide film '32. Silicon linear film thickness 5000X and epitaxial silicon film thickness 5ooo
Under the conditions of X, the width of the silicon layer 33 spread over the oxide film surface was approximately 3 μm. In this way, FIG. 3(a) is obtained.

After the formation of the gate oxide layer 34t, impurities 35 are introduced into the substrate surface in a controlled manner by means of ion implantation, and the MO
) Set to the threshold voltage of the transistor. After that, polycrystalline silicon is deposited by the CVD method and the gate electrode 36 is patterned.
CV of high*fIrS038 as a zero-order interlayer insulating film to form source/drain regions 37 by ion implantation with a dose lid of type impurity t 10'"on-" or more.
By depositing by method D and applying appropriate heat treatment,
The resistance of the gate polycrystalline silicon 36 is lowered and the surface is made flat to obtain the result shown in FIG. 93(c). After that, a contact hole 39t is formed using conventional photolithography and etching. After that, aluminum S-'lm 40 is deposited using a vacuum evaporation method to pattern a wiring electrode, and aluminum and silicon are formed in hydrogen. When alloying is performed, the finished drawing shown in FIG. 3(d) can be obtained. Must! C depending on
Protective II is deposited by VD method, and protective II is deposited on the electrode notch.
IIt-removed using photolithography and etching techniques. The transistor characteristics thus obtained were extremely good. Next, a second example will be described in detail. FIG. 4 is a diagram for explaining the manufacturing process 411I for realizing a 411I tube in which the source potential tube of two units of insulated gate field effect transistors is commonly connected to the underlying single crystal 7 silicon substrate potential. A silicon substrate 41 with a (100) orientation and a resistivity of about 0.01Ω1 is coated with a silicon substrate 41 of approximately 500Ω using a thermal oxidation method.
An acid film L [42] is formed, and patterned into a desired shape by conventional photolithography and etching.

That temporary hydrogen? Carrier gas, dichlorosilane (SiHC)
12) as a source gas, and then add chlorine gas to 80t.
Epitaxial growth of silicon is performed at a substrate temperature of 1080 cc (1080 cc) under a reduced pressure of about 100 Ω.
Boron as a P-type impurity is controlled and introduced so as to form a 0.5μtnq)II thick silicon layer 61, and in the next step, the amount of boron impurity introduced is controlled so as to obtain a resistivity t- of 1011m. A silicon layer 43f with a thickness of 10.5 am (DlK) is formed. The width of the silicon layer 43, which is silicon spread over the surface of the oxide film, is approximately 5 μm. In this way, FIG. 4 (&) is obtained. After forming the gate oxide I[44, Impurities 45 are controlled and introduced into the substrate surface by means such as ion implantation, and the desired transistor threshold voltage is set.After that, polycrystalline silicon is deposited by CVD, and gate-type tijA46 is deposited. Figure 4(b)
and then n-type impurities such as arsenic and phosphorus @ 10'
A source region 47 and a drain region 48 are formed by ion implantation with a dose lid above %m-%L. Next, an interlayer insulating film of P8G49 was deposited by the t-CVD method, and an appropriate heat treatment was performed to lower the resistance of the gate polycrystalline silicon 46 and flatten the surface, as shown in FIG. After that, a contact hole 50 is formed by ordinary photolithography and etching, and then aluminum 51 is deposited by vacuum evaporation to form a wiring pattern. 4(d), which is the finished diagram, can be obtained from the . Compared to the dimensions of a field-effect transistor, the dimensions of a unit transistor designed according to the same rules and formed by the method of the present invention are reduced by more than 4G-, and it has also been proven that the source wiring [47] is effective with high concentration. O

[Brief explanation of drawings]

Figure 1 is a schematic cross-sectional view of a polycrystalline silicon substrate type MO8 field effect transistor showing an example of a conventional ROMO8 structure, and Figure 2 is a schematic diagram emphasizing the features of the present invention in contrast to Figure 1. FIG. In the figure, 1 and 21 are silicon substrates, 2 and 22 are amorphous dielectrics, 3 and 23 are epitaxial silicon,
4 is polycrystalline silicon deposited during epitaxial growth, 24 is monocrystalline silicon deposited on an amorphous dielectric, 5#'i field oxide film, 6 and 26 are gates) [
7 and 27 are polycrystalline silicon for gate electrodes, 8
and 28Fi source/drain regions, 9 and 2Qi
10 and 30 indicate aluminum wiring electrodes, respectively. FIGS. 3 and 4 are diagrams for explaining different embodiments of the present invention, respectively, and show cross sections of elements in main processes. In the figure 3
1 is a silicon substrate, 41 Fi low resistance type silicon substrates 32 and 42 are amorphous dielectrics, 33 and 43 are high resistance P type epitaxial silicon layers, and 61 is an intermediate resistance P
type epitaxial silicon layers, 34 and 44 are gate oxide films;
37 is a source/drain region; 47 is a common source region of the two transistors; 48 is a drain region; 38 and 49 are interlayer insulating films; 39 and 50 are contact holes; 40 and Reference numeral 51 indicates aluminum wiring electrodes. Representative Patent Attorney Uchihara Uchihara Fees Figure 1 - Ikkaku - Part 2 ◆, Procedural Amendment (September 20, 1982, Own Ship, 1982) Director General of the Japanese Patent Office, 1, Indication of the Case, 1982 Patent Application No. 1058
No. 85, No. 2, am (D Name: Manufacturing method of conductor device 3, Relationship with the person making the amendment) Applicant: 5-33-1-4 Shiba, Minato-ku, Tokyo, Agent (Contact address: NEC Corporation Patent Section) 5. Column for detailed description of the invention in the specification subject to amendment Column for brief explanation of drawings in the specification Attached drawing 6. Contents of the amendment (1) Meiyusho No. 2 Contribution ag line 17 states "Attribution Toshiro”
Correct the statement ``t'' to be ``caused by t''. (From the 14th line to the 20th line on page 84 of the 21 specification, 24 is a single crystal silicon layer deposited on silicon oxide which is an amorphous electric material, 5 is a field oxide film, 6 and 26 are Gate oxide film. 7 and 27 are polycrystalline silicon for gate electrodes. 8 and 28 are source◆F rain regions, 9 and 29 are interlayer insulation 1111. For example, P2O film, io and 30 are aluminum wiring electrodes." 5 is a field oxide film, 6 and 24 are Fi gate oxide films, 7 and 25 are polycrystalline silicon for Fi gate electrodes, 8 and 2 are
6 is a source/drain region, and 9 and 27 are interlayer insulating films 9, for example, a P2O film. (3) Insert the following sentence between "in Figure 2" and "dielectric 22" on page 5, line 15 of the specification. Epitaxial growth is performed using the exposed single crystal substrate silicon as a seed, and when the epitaxial silicon film exceeds the dielectric thickness, it also forms single crystals in the lateral direction! A11l
is growing. This is corrected by saying, ``This process is carried out under a reduced pressure of about J, and hydrogen chloride is present.'' (5) On page 8, line 3 of the specification, the phrase “substrate temperature of 1080°C under reduced pressure of about 80 tons” has been replaced with “80 tons”.
rr 8 degrees of reduced pressure, substrate temperature of 950 degrees Celsius.'' (6) From line 8 to line 9 of page 8 of the specification fa, “
Under the condition of film thickness 8000A, %%S%% width is approximately 3J
Correct the statement mJ to ``Under the condition of a film thickness of 2.5 μm. 1) The width is approximately 2 μm.'' (η In specification 1s, page 9, 1g, line 18, ``with rnffl'' is corrected to ``with p-type.'' + 80 t On 4°C under reduced pressure, 1080°C base temperature t-r Hydrogen chloride tt
under reduced pressure of 50 torr@ii. 950℃ substrate temperature.'' (91 Meisho No. 10 @ Line 11 to the 13th stroke is supplemented with "0.5 μm of thick thin ore with a thickness of about 2 μm." (M)) @gll1m12m No. 9 Row 1 color iE 1
4th line [C: ``24 is a good single electrode on the amorphous dielectric material.''t'' ``5 is a field oxide film, 6 and 24 are gate oxides, 11. 7 and 25 are gate electrodes. polycrystalline silicon/, 8 and 26 are source/drain regions,
9 and 27 are corrected to ``layer insulation film association''. From the 7th line to the 8th line of page 13 of the book #ll, it says "39 and 50 are 1% 11% 40 and 51 are", "39 is contact 1-,)-40 and 50 are" and correct it. (B) The summary of drawings attached to this application, Figure 1, Figure 812, and Figure IIEA, shall be amended as shown in the attached drawings. Agent Patent Attorney Uchiho Fuga 7 Kuchi, /, □ Figure 2-! l-

Claims (1)

[Claims] In the method for manufacturing a conductor device OII, in the step of partially providing an amorphous dielectric on a single crystal silicon substrate, an impurity t is added so that the thickness of the amorphous dielectric becomes at least as thick as JP4.
) a step of depositing at least one layer of epitaxial silicon by controlling @@h- and concentration ft, a step of forming a gate insulating film, and a step of depositing a gate region/source region on the single crystal silicon substrate on the amorphous dielectric. , a method for manufacturing a semiconductor device comprising the step of providing at least one region of a drain region.