JPS5878493A - Printed circuit board - Google Patents

Printed circuit board

Info

Publication number
JPS5878493A
JPS5878493A JP17748981A JP17748981A JPS5878493A JP S5878493 A JPS5878493 A JP S5878493A JP 17748981 A JP17748981 A JP 17748981A JP 17748981 A JP17748981 A JP 17748981A JP S5878493 A JPS5878493 A JP S5878493A
Authority
JP
Japan
Prior art keywords
oxide
wiring board
printed wiring
plating
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17748981A
Other languages
Japanese (ja)
Inventor
赤沢 正史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suwa Seikosha KK
Original Assignee
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suwa Seikosha KK filed Critical Suwa Seikosha KK
Priority to JP17748981A priority Critical patent/JPS5878493A/en
Publication of JPS5878493A publication Critical patent/JPS5878493A/en
Pending legal-status Critical Current

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  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 この発明は新規なフルアディティブ法によるプリン)配
線板に関するもので、更には製造コストが安価で、放熱
性が良く、高密度実装が可能なプリント配線板に関する
ものである。
[Detailed Description of the Invention] This invention relates to a printed wiring board manufactured using a novel fully additive method, and further relates to a printed wiring board that is inexpensive to manufacture, has good heat dissipation, and can be mounted at high density. .

従来からプリント配線板には種々の材料が用いられ、そ
の製造方法も多紋にわたっている。現在の主流はガラス
エlキシ積層板あるいは紙フエノール板に鋼箔を張った
基板をエツチングして回路パターンを形成するサブFラ
クティプ法である。
Conventionally, various materials have been used for printed wiring boards, and there are many different manufacturing methods. The current mainstream method is the sub-F lactip method, in which a circuit pattern is formed by etching a substrate made of a glass eloxy laminate or a paper phenol plate covered with steel foil.

しかしこの方法は、エツチングパターンのアンダーカッ
Fの問題、熱伝導率の低い基板材料に起因する放熱不良
の間層、爾箔の厚みやレジス)膜の厚みでパターンの精
度が限定されるため高密度配線ができないなど橡々な性
能上の問題に加え、製造工程が長く、ドライフィルム等
のレジスト材料を使用するためコスシ高になるという問
題を有している。
However, this method requires high accuracy because the pattern accuracy is limited by the problem of undercutting in the etching pattern, poor heat dissipation due to the substrate material with low thermal conductivity, and the thickness of the etching foil and resist film. In addition to serious performance problems such as the inability to perform high-density wiring, there are also problems in that the manufacturing process is long and the cost is high because a resist material such as a dry film is used.

これらの欠点を改善する方法として、基板の所質パター
ン部にのみ選択的に無電解メ1ツ′キ、を施こすアディ
ティブ法が検討されている。00−4法、Pト1法、フ
ォトフォー五法、P8MI)法などいくつかのアディテ
ィブプ薗セスが発表され実用化されている方法もある。
As a method to improve these drawbacks, an additive method is being considered in which electroless plating is selectively applied only to predetermined pattern portions of the substrate. Several additive processes have been announced and put into practical use, such as the 00-4 method, the P-1 method, the Photofor-5 method, and the P8MI) method.

これらの方法によるとアンダーカッFがない、高密度配
線が可能、低コストである。量産性にすぐれるといった
アディフィププロセスの利点の内いくつかは満足させる
ことができる。しかしながら現在検討されているいかな
るアディティブ法を用いても高密度実装にともなう放熱
性の問題は解決できない。また真流のアディティブ法で
はメッキのかぶりによるツイン精度不良、パターンの密
着不良が大きな間■として残っており製造歩留りが悪い
ため結局低コスト化につながらない欠点を有している。
According to these methods, there is no undercut F, high-density wiring is possible, and the cost is low. Some of the advantages of the Adifip process, such as excellent mass productivity, can be satisfied. However, no matter what additive methods are currently being considered, the heat dissipation problems associated with high-density packaging cannot be solved. In addition, the true flow additive method has the disadvantage that poor twin precision due to plating fog and poor pattern adhesion remain as major gaps, resulting in poor manufacturing yield and ultimately not leading to cost reduction.

本発明はこのような欠点を改良し、アディティブ法が本
来もうている上記の利点を全て満足し、なお且つ放熱性
に優れた適用範囲の広いプリント配線板を提供するもの
である。
The present invention improves these drawbacks, and provides a printed wiring board that satisfies all of the above-mentioned advantages inherent in the additive method, has excellent heat dissipation properties, and has a wide range of applications.

製造工程順に本発明の詳細な説明する。まず基板の材料
には金属を使用する。金属の材質は何で点から一般には
スチール、アル識ニウムなどのα1〜10■厚のシーt
もしくは7−プ材が適する。
The present invention will be described in detail in the order of manufacturing steps. First, metal is used as the substrate material. What is the material of the metal?In general, it is a sheet of α1~10cm thick such as steel or aluminum.
Alternatively, 7-ply material is suitable.

これらの金属シートあるいはフープは最初にパンチング
で大抜き加工する。スルーホール穴、ガイド穴、TO用
大、その他必要な部分を打抜く。また場合によってはプ
レスによりて段差をつけたり折り曲げ加工をし七もかま
わない0次にこれらの金属材料の表面を絶縁処理するた
め電着塗装する本発明の第1の特徴は、この電着塗料中
に酸化チタン、酸化亜鉛、酸化スズ、酸化インジウム。
These metal sheets or hoops are first punched into large dimensions. Punch out through holes, guide holes, TO size, and other necessary parts. The first feature of the present invention is that the surface of these metal materials is electrodeposited for insulation treatment. Titanium oxide, zinc oxide, tin oxide, and indium oxide.

酸化アル1晶ウム、酸化タンタル、酸化ジルコニウム、
*化ニオブ等の紫外線照射によって表面が還元性を有す
る%型半導体粉末を分散して樹脂と同時に析出させる点
にある。これらの酸化物は光照射によって表面の酸素が
欠乏し、還元能力を有することは古くから知られている
。特に酸化チタンは還元性が強いため本方法に適する。
Almonium oxide, tantalum oxide, zirconium oxide,
*The method consists in dispersing %-type semiconductor powder such as niobium oxide whose surface has reducing properties by irradiating it with ultraviolet rays and precipitating it simultaneously with the resin. It has been known for a long time that these oxides have a reducing ability when the surface of these oxides is depleted of oxygen by light irradiation. Titanium oxide is particularly suitable for this method because it has strong reducing properties.

一般の無電解メッキではメッキ核となる金属微粒子を還
元析出するため2価のスズイオンを吸着させるセンシタ
イジングの工程が必要であるが、本発明ではセンシタイ
ジング工程は必要ない。また光の照射部のみ還元性を有
するためマスクを通して露光すれば所望のパターンが得
られ、7オ)レジス)の鎗布、硬化、剥離等の工程は不
必要でしかもレジスト膜の厚みが無いためアンダーカッ
ト、オーバーハング等の欠陥のない高密度、パターンが
形成できる。実験の結果、露呈半導体粉末の粒径は小さ
い程、また塗膜中の容積比は大きい程効果が大きいこと
がわかりた。好ましくは粒径1μ以下の粉末を塗料固形
分中の容積で20−以上含有するような電着塗料を調合
するのが良い、なお電着塗料のマトリクス樹脂はアニオ
ンのぎりブタジェン系とカチオンのエポキシ系が秀れて
おり、フレキシブル基板には可とり性のあるポリブタジ
ェン、リジッド基板には耐湿性の良く硬い工lキシが適
している。いずれも絶縁性を保障し、浮遊春量を小さく
するためsOμ以上の厚付が必要であり、電着電圧は1
50v以上を必要とする。また一般O電着塗料では電着
後加熱硬化する時に特に基板のエツジ部の塗料が流れて
膜厚が薄くなり絶縁不良を生ずる欠点がありたが、本発
明のように酸化物輪車を多量に分散した電着液ではエツ
ジ部の塗料  ′流れな防止することができ絶縁の信頼
性が向上する。
In general electroless plating, a sensitizing step is required to adsorb divalent tin ions in order to reduce and precipitate fine metal particles that serve as plating nuclei, but the present invention does not require a sensitizing step. In addition, since only the irradiated area has reducibility, the desired pattern can be obtained by exposing through a mask, and the steps of 7e) rolling, curing, and peeling of the resist are unnecessary, and there is no thickness of the resist film. High-density patterns can be formed without defects such as undercuts and overhangs. As a result of experiments, it was found that the smaller the particle size of the exposed semiconductor powder and the larger the volume ratio in the coating film, the greater the effect. It is preferable to prepare an electrodeposition paint that contains powder with a particle size of 1 μm or less by volume of 20 or more in the solid content of the paint.The matrix resin of the electrodeposition paint is an anionic butadiene-based resin and a cationic epoxy resin. Polybutadiene, which is flexible, is suitable for flexible substrates, and polybutadiene, which is hard and has good moisture resistance, is suitable for rigid substrates. Both require a thickness of sOμ or more to ensure insulation and reduce the amount of floating springs, and the electrodeposition voltage is 1
Requires 50v or more. In addition, general O electrodeposition paints have the disadvantage that when heated and cured after electrodeposition, the paint flows especially at the edges of the substrate, resulting in thin film thickness and poor insulation, but as in the present invention, a large amount of oxide wheel Electrodeposition liquid dispersed in the electrode layer prevents the paint from flowing around the edges, improving the reliability of the insulation.

次に金属コアの表面を絶縁処理した基板に、光照射によ
って選択的に無電解メッキをする工程に入る。まずメッ
キの密着性を確保するため電着塗膜表面を通常のクーム
ー硫酸混液でエツチング粗化する。ビー羨強度”L 5
 kg / as程度を得るためには50℃、2分I!
度のエツチングで充分である。
Next, the process of selectively electroless plating the substrate, which has had the surface of the metal core insulated, using light irradiation, begins. First, in order to ensure adhesion of the plating, the surface of the electrodeposited coating is roughened by etching with a common Coumu sulfuric acid mixture. Bee envy strength”L 5
To obtain about kg/as, 50℃, 2 minutes I!
A degree of etching is sufficient.

エツチング、洗浄、乾燥11.ガラスもしくは石英マス
クを通して紫外mて露光する。酸化チタンの場合、還元
性を有する反応に必要な光の波長は、4oo−以下であ
るが露光時間を短縮するため2So−300mm()波
長を含む光源で露光するのが好重しい、+の場合マスク
には石英ガラスが必要となる。露光後、通常のアクチベ
ーシ冒ンを行なって露光部にメッキ核となる金属微粒子
を析出させる。アクチペーターには塩化パラジウムの希
薄水溶液が適している。この後無電解鋼メッキあるいは
ニッケルメッキによりて導体パターンを形成し、必要に
応じて電解鋼メッキで厚付メッキをしたり、ボンディン
グ用金メッキを施こせばプリント配線板が完成する。
Etching, washing, drying 11. Expose to ultraviolet light through a glass or quartz mask. In the case of titanium oxide, the wavelength of light necessary for a reducing reaction is 400 mm or less, but in order to shorten the exposure time, it is preferable to expose with a light source that includes a wavelength of 2 So-300 mm (). In this case, quartz glass is required for the mask. After exposure, normal activation is performed to precipitate fine metal particles that will become plating nuclei in the exposed area. A dilute aqueous solution of palladium chloride is suitable for the activator. Thereafter, a conductor pattern is formed by electroless steel plating or nickel plating, and if necessary, thick electrolytic steel plating or gold plating for bonding is applied to complete the printed wiring board.

以上のような工程でつくられたプリント配線板の特徴を
、従来から行なわれているサブトラクティブ法やアディ
ティブ法と比較して整理すると、(1)基板材料が安価
で、しかも大抜きやプレスの機械加工が容易で、またパ
ターニングの工程が短いので製造コスFが大巾にダウン
できる。
Comparing the characteristics of printed wiring boards made using the above processes with the conventional subtractive and additive methods, we can summarize the following: (1) The board material is inexpensive, and it is easy to use for large punching and pressing. Since machining is easy and the patterning process is short, manufacturing cost F can be significantly reduced.

(2)エツチングをしない光選択メッキのため、アンダ
ーカットやオーバーハング等の不良がない。
(2) Optical selective plating without etching eliminates defects such as undercuts and overhangs.

(1)レジストを使用しないため、最小2μ程度重でO
微細パターンが可能である。
(1) Since no resist is used, the O
Fine patterns are possible.

(4)メタルコアで放熱性が良く高密度実装に適する拳 (5)7−プ材料を使った連続大量生産と、シート材料
を使った少量多種生産のいずれにも適する。
(4) The metal core has good heat dissipation and is suitable for high-density packaging. (5) It is suitable for both continuous mass production using 7-ply material and low-volume multi-product production using sheet material.

ある、そのためスルーホールの信頼性も高い。Therefore, the reliability of the through hole is also high.

このようにメタルコア、S型半導体粉末を分散した電着
論科、光選択メッキを組み合わせることによりて、低コ
メFて品質の秀れた応用範囲の広いプリント配線板が製
造できる。次に典禿的な実施例を述べる。
By combining the metal core, electrodeposition with S-type semiconductor powder dispersed therein, and photo-selective plating, it is possible to manufacture a printed wiring board with a wide range of applications, which has low heat flux and excellent quality. Next, a typical example will be described.

〈実施例〉 フープ材を基材に使用して腕時計用プリント配線板を一
貫加工した。厚み(L15■のスチール((L 8 %
 0ff) kmスルー*−ル穴、 I O穴、 カ4
ド穴をパンチングで打抜き、脱脂洗浄後全面に電着m*
をした。Ik料樹脂は)i、720%のカチオンエl午
シ系で、電膜中のam分の25容量弧が酸化チタンにな
るように塗料を調合した。酸化チタンは粒@a2〜r1
5μのアナターゼ製粉末を使用した。20℃で2501
,5分電着後、水洗して180℃、30分ベーキングし
て硬化させた。
<Example> A printed wiring board for a wristwatch was manufactured in an integrated manner using a hoop material as a base material. Thickness (L 15■ steel ((L 8%)
0ff) km through hole, IO hole, 4
Holes are punched out, and electrodeposited on the entire surface after degreasing and cleaning.
Did. The Ik material resin was a 720% cationic resin, and the paint was prepared so that 25 capacitance arcs of the am component in the electrolytic film were titanium oxide. Titanium oxide is grain @a2~r1
5μ powder made from anatase was used. 2501 at 20℃
After electrodeposition for 5 minutes, it was washed with water and baked at 180° C. for 30 minutes to harden it.

膜厚は平担部で約50μ、エツジ部ではSO〜35se
lKである0次に飽和り四ム酸と硫蒙混液中で40℃、
2分表面をエツチング粗化した。粗面0段差は約3μで
均一であった。水洗、中和、乾燥後、波長約250鱈の
紫外線露光機で2秒照射した。マスクは石英製で基板と
コンタクトした。露光後直ちに塩化パラジウムの1−水
滴液中に20℃で2分浸漬し、軽く水洗後無電解ニッケ
ルメッキ液中で50℃、5分メッキを行った。紫外線照
射部にのみニッケルのメッキパターンを得た。パターン
の最小線巾と線間隔はともに50μで、配線切れ、リー
ク等の欠陥は1−以下であった。工、ケルパターンの上
に直接電解で金を05μメツキして配線板を完成させた
。工0をボンディング実装後の耐環境試験では良好な結
果を得た。また配線板の製造コストは、従来の銅張ガラ
エボ基板を7オ)工程でパターニングするサブトラクテ
ィブ法に較べて約1/2と大巾なコストダウンが可能と
なった。
The film thickness is approximately 50μ on the flat part, and SO ~ 35μ on the edge part.
40°C in a mixture of 0-order saturated tetramuic acid and sulfuric acid at lK,
The surface was roughened by etching for 2 minutes. The zero step difference on the rough surface was approximately 3μ and uniform. After washing with water, neutralizing, and drying, it was irradiated with ultraviolet rays at a wavelength of about 250 for 2 seconds using an exposure machine. The mask was made of quartz and was in contact with the substrate. Immediately after exposure, it was immersed in a 1-water droplet solution of palladium chloride at 20°C for 2 minutes, and after being lightly washed with water, it was plated in an electroless nickel plating solution at 50°C for 5 minutes. A nickel plating pattern was obtained only in the ultraviolet irradiated area. The minimum line width and line spacing of the pattern were both 50 μm, and defects such as wire breaks and leaks were 1- or less. The wiring board was completed by directly electrolytically plating 05μ gold on the Kel pattern. Good results were obtained in the environmental resistance test after bonding and mounting. Furthermore, the manufacturing cost of the wiring board can be significantly reduced to about 1/2 compared to the subtractive method in which a conventional copper-clad Gala Evo board is patterned in 7 steps.

以上 手続補正書(自発) 昭和57年11月 8日 特許庁長官殿 昭和56年特許願第177489号 2、発明の名称 プ゛りント配總極 3、補正をする者 伺[8役中村恒也 4、代理人 手続補正書 1.明細書 5員6行 「である、量産性」とめるを 「である1重重性」に補正する。that's all Procedural amendment (voluntary) November 8, 1982 Commissioner of the Patent Office 1981 Patent Application No. 177489 2. Name of the invention Print distribution pole 3. Person who makes corrections Visit [8th role Tsuneya Nakamura 4. Agent Procedural amendment 1. Specification: 5 members, 6 lines ``It is mass production''. Corrected to ``uniplexity''.

2 明細書 41I6行 (−TO用用穴上めるを 「IO用穴J Kl’l正する、 五 明細書 7頁下から6行 「最小2μ橿度」とめるを 「最小20μ程簾」と補正する。2 Specification 41I line 6 (-Place the hole for TO "Correct IO hole J Kl'l, 5. Specification 6 lines from the bottom of page 7 "Minimum 2μ radius" stop Correct it to ``minimum 20μ blind''.

4、明細書 8頁15行 「塗料橘脂は4v201!Jとめるを 「塗料樹脂はN Y 20 %Jと補正する。4. Specification page 8 line 15 ``Paint orange fat is 4v201!J stop. “The paint resin is corrected to N Y 20% J.

五 明細書 9NS行 「、波長約2501111Jとめるを [波長250〜450 nmJと補正する。V. Statement line 9NS ``The wavelength is about 2501111J. [Corrected to wavelength 250-450 nmJ.

瓜 明細書 9@6行、8行 「ニッケル」とめる會 [銅1と補正する。Melon specification 9 @ line 6, line 8 "Nickel" stop meeting [Corrected to copper 1.

1 明細419頁7行 「5分メッキを行なっり、」とめるt 「1時間メッキを行なった・」と補正する。1 Details page 419 line 7 ``Perform plating for 5 minutes,'' then stop. Correct it by saying, ``Plating was done for 1 hour.''

a 明細書 917行 [液中で50℃、−1とらるを 「液中で25℃、」と補正する。a Specification line 917 [50℃ in liquid, -1 toraru Correct it to ``25℃ in liquid.''

以 を 代理人 鍛 上   務More Agent training management

Claims (1)

【特許請求の範囲】[Claims] 金属基材に電着塗装によって電気的絶縁処理を施こし、
その上に導体パターンを形成するプリント配線板におい
て、電着塗料中に酸化チタン、酸化亜鉛、酸化スズ、酸
化インジウム、酸化アルミニウム、酸化タンタル、酸化
ジルコニウム等の光照射によって表面が還元性を有する
%臘牛導体粉末を分散して樹脂と同時に電着させて絶縁
属を廖成し、しかる絶縁塗膜上の導体が必要な部分にの
み紫外線を含む光を照射することによってアクチペータ
ーを選択的に還元析出させ、無電解メッキに選択性を付
与して導体パターンを形成したことを特徴とするプリン
ト配線板。
Electrical insulation treatment is applied to the metal base material by electrodeposition coating,
In a printed wiring board on which a conductive pattern is formed, the surface has a reducing property when exposed to light such as titanium oxide, zinc oxide, tin oxide, indium oxide, aluminum oxide, tantalum oxide, zirconium oxide, etc. in the electrodeposition paint. The activator is selectively activated by dispersing the conductor powder and electrodepositing it simultaneously with the resin to form an insulating layer, and then irradiating light containing ultraviolet light only to the areas on the insulating coating where the conductor is needed. A printed wiring board characterized in that a conductor pattern is formed by reduction deposition and imparting selectivity to electroless plating.
JP17748981A 1981-11-05 1981-11-05 Printed circuit board Pending JPS5878493A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17748981A JPS5878493A (en) 1981-11-05 1981-11-05 Printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17748981A JPS5878493A (en) 1981-11-05 1981-11-05 Printed circuit board

Publications (1)

Publication Number Publication Date
JPS5878493A true JPS5878493A (en) 1983-05-12

Family

ID=16031789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17748981A Pending JPS5878493A (en) 1981-11-05 1981-11-05 Printed circuit board

Country Status (1)

Country Link
JP (1) JPS5878493A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62214696A (en) * 1986-03-15 1987-09-21 松下電工株式会社 Printed wiring board
JP2008075890A (en) * 2006-09-19 2008-04-03 Matsushita Electric Ind Co Ltd Refrigerator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5085876A (en) * 1973-11-29 1975-07-10
JPS54108265A (en) * 1978-02-13 1979-08-24 Nippon Telegraph & Telephone Method of forming circuit on electrocoated metal board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5085876A (en) * 1973-11-29 1975-07-10
JPS54108265A (en) * 1978-02-13 1979-08-24 Nippon Telegraph & Telephone Method of forming circuit on electrocoated metal board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62214696A (en) * 1986-03-15 1987-09-21 松下電工株式会社 Printed wiring board
JPH0455558B2 (en) * 1986-03-15 1992-09-03 Matsushita Electric Works Ltd
JP2008075890A (en) * 2006-09-19 2008-04-03 Matsushita Electric Ind Co Ltd Refrigerator

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