JPS5878465A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To offer the manufacturing method of a semiconductor, in which a gate electrode does not come off and the degradation in withstanding voltage of said electrode can be prevented. CONSTITUTION:An SiO2 film 22 is formed on a p type silicon substrate 21 at a relatively high temperature. Thereafter, an MoSi film 23 is formed on said SiO2 film 22 by an evaporating method. Then a resist pattern 24 is formed on said MoSi film 23 by a photoetching method. It is removed by an ion etching method and a gate electrode 25 is formed. Then the resist pattern 24 is removed. With the gate electrode 25 as a mask, the SiO2 film 22 is etched by aqueous solution of NH4F and the like, and a gate insulating film 26 is formed. Then n<+> type source and drain regions 27 and 28 are formed by a self-aligning method. Thereafter a polycrystal silicon film 29 is formed by a CVD method at a relatively low temperature (550-650 deg.C). Then heat treatment of said polycrystal silicon film 29 is performed in an oxidizing atmosphere at a relatively high temperature (800-1,100 deg.C), so that the film 29 is transformed into a thermal oxide film 30. An interlayer insulating film 31 is further coated on said thermal oxide film 30 by a CVD method.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor f! 0 Regarding improvement of the manufacturing method of turtles Conventionally, semiconductor # devices such as insulated gate field effect transistors (MO8FET) have been manufactured using 141111(a) to (
d) is manufactured as shown in FIG. ! For example, a 5 lot film 2 is formed by relatively eddy current, an electrode material film such as molybdenum silinide lII (Most) is formed on this stow film 2, and this Mo5t is formed by photolithography. A resist pattern 4 is formed on the resist pattern 4 (see 1st tg (a)' tlJ).Next, the ζO resist pattern 4 is masked and
Etching and removing 81jllJ and gate IIIL love 5
(Illustrated in FIG. 2B) 0 Then, the resist pattern 4 is removed, and the gate electrode 5t-! 81.
A gate insulating film 6 is formed by etching away the gate electrode 2, and then an n-type non-layer 1 is used as a gate voltage 5t mask.
Source/drain regions 7.8 made of n+ are formed in a self-aligned manner on the fitting surface of the substrate 1 by ion-implanting one substance, for example, arsenic (
IW, 1m (c) shown). Subsequently, a Hatoma insulation layer P is applied to the semiconductor substrate 1 including the gate electrode 5 and the source/drain regions 1.8 at a low temperature by the CVD method.
After that, contact holes (not shown) to make simultaneous contact with the gate electrode 5 and source/drain regions 2.8 are shaped, and desired wiring (not shown) is performed to complete the MOSFET.
ET is manufactured (as shown in the same figure (d)). - However, the insulating field effect transistor formed as described above had the following drawbacks.

That is, because of the bud-per-etching when etching the StO layer 2 using the gate electrode 5 as a mask, the end mxo of the gate insulating film 6 is formed inside the end 11 of the gate electrode 5, so-called Overhang @XX occurs.

This over-eight part 114% could not be deposited in the lead metal with the layer-related film formed by the CVD method.
As shown in 6), the sky-@II is formed into the form Iit, and this)
The rviMOIF obtained by reducing the pressure resistance of Dart Kame-I
In order to improve the breakdown voltage of the gate voltage 1kJ, the source/drain region 1. After shaping ξ, a thermal oxidation layer is formed on the source/drain regions 1, 1'' and the gate layer 11111 by heat treatment at high temperature in an oxidizing atmosphere. If the electrode material film is a polycrystalline silicon film, it can prevent the breakdown voltage of the electrode I from decreasing, but if it is a high-melting point metal or a ζt>*tso* compound, it can directly oxidize the dirt charge Mi! High-temperature heat treatment at high temperature is used for - i.e., gate electrode &J$J611#KA
11Kml (t, L, corroded 9〉, thermal strain due to the difference between electric tikJ and dirt insulating film C and O thermal expansion coefficient O - IIX!
1. ) and locally insulate the gate electrode 50
N- to - Kurenai is four.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor II device that can prevent a drop in breakdown voltage of the armpit electrode without causing peeling of the gate electrode. It is.

That is, the process of sequentially forming an insulating film and a metal material film on the semiconductor substrate of the present invention Fi, the process of forming a gate electrode by buttering this electrode material film, and then forming a gate electrode. forming a gate insulating film by selectively etching the insulating film using the electrode as a mask; forming a second conductive source/drain region I on the surface of the semiconductor substrate by exposing the gate 11; - a step of forming a non-single-crystal silicon layer on a semiconductor substrate that meets a source/drain region; and a step of heat-treating the non-single-crystal silicon layer in an oxidizing atmosphere to convert it into oxide lI&. It is characterized by nine things.

1) The electrode material film for iK includes molybdenum, tungsten, titanium, tantalum JC1 high melting point metals and these metals O! ! Examples include firefly lipdendi9tide, tungsten silinide, etc., which are chemical compounds.

Examples of the non-single crystal silicon material used in the present invention include a polycrystalline silicon film, an impurity-doped polycrystalline silicon film, and an amorphous silicon film. It is preferable to use a polycrystalline silicon film formed by the CVD method at 5sO to 6sO ℃ as a non-early crystalline silicon film. It is possible to reduce the overhang gap that is formed. Further, the temperature range lI when forming a thermal oxidation layer by annealing the polycrystalline silicon film is preferably 800 to 1100°C. When the temperature exceeds this level, O# leakage occurs from the gate insulating film of the gate electrode at 14 Vh.

Hereinafter, the present invention will be described with reference to FIGS. 2(1) to (•) when applied to Mo2 FIST K.

(1) First, an 810° film J1 is formed on the Pa11 silicon substrate xx with a specific width of about 100°, and then KM 8111A11 is formed on this 810° film 11 by a vapor deposition method. next,
A resist pattern 24 is formed on this Mo81JIkzs by photolithography (as shown in FIG. 2(a)). Next-
Then, using this resist pattern 24 as a mask, the Me
Sl gland 21 is removed (by reactive ion etching method),
Form a gate electrode @1g (P!U wholesaler (b) shown).

CM) Next, after removing the resist pattern 24, the 810m film 22 is coated with N114 using the gate electrode 25 as a mask.
The gate insulating film 2 is etched with F*flj liquid or the like.
6 is formed, and using the same electrode z5 as a mask, for example, arsenic is diffused or ion-implanted into the surface of the substrate 21 to form a source-drain region zy, is of self-aligned Knfm with respect to the gate electrode &jJK ( fj1 diagram (e) diagram)
.

(...) Next, polycrystalline silicon j[2# is formed on the semiconductor substrate 21 including the gate electrode 26 and the solar drain regions zy and is by a CVD method at a relatively low temperature (550 to 650°C). The polycrystalline silicon film 29 is then heated to a relatively high temperature (800 to 1
A thermal oxide film 30 is formed by heat treatment in an oxidizing atmosphere (100°C).
change to KCV on this heat-cured film Jo
The flk conversion 81 is carried out at low temperature by method D. This bale, gate electrode 41Kis and source/drain region sr
, za are formed, and a desired An arrangement (not shown) is performed to form a contact hole k (not shown) to make electrical contact with M.
Manufactures OS FETs. (Same figure (・)-shown).

The above manufacturing method has the following advantages.

(Support) Polycrystalline silicon film 2# formed by CVD method! Because the weldability of the R difference part is improved, Fig. 2 (d) K
As shown, when the substrate 11 containing 25 gate electrodes is covered with 1iIK, the end sJ of the gate electrode z5! A hole is formed in which the overhang portion IJ formed in the vicinity is hermetically filled with the polycrystalline silicon film 2#. The polycrystalline silicon group 2 with the group @xr*mK that meets the 25 mag.
I! By completely changing 7g from JllK to thermal oxidation 80, the air below the overhang ssJ can be wrinkled by the thermal oxide film SO ◇Therefore, a drop in the breakdown voltage of the gate turtle @xi can be prevented. can do.

(a) As in the conventional method, the oxidation of the gate 1klk 25 itself can be minimized by thermally oxidizing the polycrystalline silicon film 29 on which the gate IIL 25 is laminated, instead of directly thermally oxidizing the gate electrode. Abnormal oxidation of gate voltage @3s can be prevented. Refreshingly, the formation of polycrystalline silicon 1129 takes place at a relatively low temperature of 550 to 650°C, and the reaction is a deposition reaction.
Peeling from the gate insulating film 2g and polycrystalline silicon film 2
It is possible to prevent # from peeling off from the substrate 11.
During thermal oxidation at a relatively high temperature of ~1100°C, Gu) I
Since the polycrystalline silicon group 29 which is in contact with the top of the IE electrode 2 presses the gate electrode 25, peeling can be prevented.

(fA) In order to completely thermally oxidize the overhang part 3JK embedded 9 polycrystalline silicon 2p, use a plane 21 (・)
As shown in FIG. - The withstand voltage of the drain regions z't and is can be further improved, and the parasitic capacitance between them can be reduced, and the resulting MOS FET can be interlocked.

In addition, in the above embodiment, the time for thermally oxidizing the polycrystalline silicon film is ff0 to completely thermally oxidize the polycrystalline silicon film.
The oxidizing atmosphere may be dry oxygen, water vapor, or hydrogen chloride. However, the thermal oxide film may be used as the interlayer insulating film without using such an interlayer insulating film.

In the *example above, after forming the source/drain region, a polycrystalline silicon layer is formed on the semiconductor substrate including that region, but before forming the source/drain region, the semiconductor substrate and the entire surface are Even if a source/drain region is formed in a self-aligned manner by covering a substrate with crystalline silicon and performing diffusion or ion implantation through that film, as long as the polycrystalline silicon film is converted into a thermal oxide film, I can't help but ask.

As described above, the present invention provides semiconductors such as highly reliable insulated gate tIlt field effect transistors that can prevent a drop in breakdown voltage of a gate electrode without causing peeling during local abnormal oxidation of the gate electrode. It is possible to provide a method for manufacturing an apparatus O1l.

[Brief explanation of drawings]

111i 1 m (a) ~ (d) U conventional MOS F
Cross-sectional views showing ET during production, Nos. 26!0(a)-(
・) is a MOS FET which is an example of the present invention.
It is a cutting diagram shown in the manufacturing work @ coffee. JZ, p, il□, 2 groups-”% J J -810m
Film, 23... Mo5t film, 25... Gate electrode, 2
6... goo) i, membrane, 21... source region, 28
...Drain region, 29...Polycrystalline silicon group, 1
0...Temperature flower-1l J 810 layer orchid insulation sz-
fmm, xx-overhang part. Applicant's agent ff! ±- Takehiko Suzue Figure 1 Figure 2 IlI

Claims (2)

[Claims] (1) An insulating film and an electrode material are sequentially formed on a semiconductor substrate of 1[m], and a lever gate is formed by patterning this electrode material to form a pole on the gate 1;
Electrodes! A step of selectively etching the insulating film as a step to form a gate insulating film, a step of forming a source and drain layer made of high-density conductivity on the surface of the unnecessary semiconductor substrate, and a step of forming the gate-pole and source/drain regions. manufacturing a semiconductor device comprising the steps of: forming a non-single crystal silicon film on a semiconductor substrate containing the silicon film; and converting the non-single crystal silicon film into oxide by heat-treating the non-single crystal silicon film in a chlorinating atmosphere. Method. . (2) A method for manufacturing a semiconductor device according to claim (1), wherein the electrode material film is made of a metal with a melting point or a silicide of this gold ingot. CVD at 650℃
A polycrystalline silicon film formed by a polycrystalline silicon film according to the method 19 and thermally saponified at imt yoke of t-5oo to 1100°C! l plane (1)
Method 0 of manufacturing a semiconductor device according to Item 1