JPS5877072U - Substrate for mounting semiconductor elements - Google Patents

Substrate for mounting semiconductor elements

Info

Publication number
JPS5877072U
JPS5877072U JP17103981U JP17103981U JPS5877072U JP S5877072 U JPS5877072 U JP S5877072U JP 17103981 U JP17103981 U JP 17103981U JP 17103981 U JP17103981 U JP 17103981U JP S5877072 U JPS5877072 U JP S5877072U
Authority
JP
Japan
Prior art keywords
conductive part
row
insertion holes
conductive
pin insertion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17103981U
Other languages
Japanese (ja)
Inventor
貞広 昌利
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP17103981U priority Critical patent/JPS5877072U/en
Publication of JPS5877072U publication Critical patent/JPS5877072U/en
Pending legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は従来の装置を示す概略図、第3図
はデュアルインラインタイプの半導体素子を示す概略図
でaは正面図、bは側面図、Cは下面図である。第4図
はこの考案の一実施例を示す概略図、第5図は基板構成
を示す概略図である。 図中、1はデュアルインラインタイプの半導体素子本体
、3.4. 5. 6は導電部列、51゜61は導電部
、52.53および62.63はピン挿入穴、7は基板
、11は端子である。なお同一符号は同一または相当部
分を示す。
1 and 2 are schematic diagrams showing a conventional device, and FIG. 3 is a schematic diagram showing a dual in-line type semiconductor element, in which a is a front view, b is a side view, and c is a bottom view. FIG. 4 is a schematic diagram showing an embodiment of this invention, and FIG. 5 is a schematic diagram showing the structure of the substrate. In the figure, 1 is a dual in-line type semiconductor element body, 3.4. 5. Reference numeral 6 designates a conductive part array, 51.degree. 61 a conductive part, 52.53 and 62.63 pin insertion holes, 7 a substrate, and 11 a terminal. Note that the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】 1 デュアルインラインタイプの半導体素子を装着する
基板において、上記半導体素子の一方のピン列に対応し
て所定間隔で直線状に配設された複数の導電部からなる
第1の導電部列および上記半導体素子の他方のピン列に
対応して所定間隔で直線状に配設された複数の導電部か
らなる第2の導電部列を設け、上記導電部列の各導電部
には、対向する導電部列の方向に所定寸法離隔した少な
くとも2個のピン挿入穴を、各導電部の対応するピン挿
入穴がそれぞれ直線上に位置するように配設すると共に
、第1の導電部列の各導電部に形成されたピン挿入穴の
離隔寸法と第2の導電部列の各導電部に形成されたピン
挿入穴の離隔寸法とを相異させたことを特徴とする半導
体素子の装着用基板。 2 両導電部列の各導電部にそれぞれ2個のピン挿入穴
を設けることを特徴とする実用新案登録請求の範囲第1
項記載の半導体素子の装着用基板。
[Claims for Utility Model Registration] 1. In a board on which a dual-in-line type semiconductor element is mounted, a plurality of conductive parts arranged linearly at predetermined intervals corresponding to one row of pins of the semiconductor element are provided. A second conductive part row consisting of a plurality of conductive parts linearly arranged at predetermined intervals is provided corresponding to the first conductive part row and the other pin row of the semiconductor element, and each conductive part row of the conductive part row is At least two pin insertion holes spaced apart by a predetermined dimension in the direction of the opposing rows of conductive parts are arranged in the part so that the corresponding pin insertion holes of each conductive part are located on a straight line, and the first The distance between the pin insertion holes formed in each conductive part of the second conductive part row is different from the distance between the pin insertion holes formed in each conductive part of the second conductive part row. A substrate for mounting semiconductor elements. 2 Utility model registration claim 1 characterized in that each conductive part of both conductive part rows is provided with two pin insertion holes, respectively.
A substrate for mounting a semiconductor element as described in 1.
JP17103981U 1981-11-16 1981-11-16 Substrate for mounting semiconductor elements Pending JPS5877072U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17103981U JPS5877072U (en) 1981-11-16 1981-11-16 Substrate for mounting semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17103981U JPS5877072U (en) 1981-11-16 1981-11-16 Substrate for mounting semiconductor elements

Publications (1)

Publication Number Publication Date
JPS5877072U true JPS5877072U (en) 1983-05-24

Family

ID=29962979

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17103981U Pending JPS5877072U (en) 1981-11-16 1981-11-16 Substrate for mounting semiconductor elements

Country Status (1)

Country Link
JP (1) JPS5877072U (en)

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