JPS5875256A - 実行命令遂行状態のモニタ方式 - Google Patents
実行命令遂行状態のモニタ方式Info
- Publication number
- JPS5875256A JPS5875256A JP56171498A JP17149881A JPS5875256A JP S5875256 A JPS5875256 A JP S5875256A JP 56171498 A JP56171498 A JP 56171498A JP 17149881 A JP17149881 A JP 17149881A JP S5875256 A JPS5875256 A JP S5875256A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- execution
- unit
- common bus
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Prevention of errors by analysis, debugging or testing of software
- G06F11/362—Debugging of software
- G06F11/3648—Debugging of software using additional hardware
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/348—Circuit details, i.e. tracer hardware
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/3471—Address tracing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Debugging And Monitoring (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56171498A JPS5875256A (ja) | 1981-10-28 | 1981-10-28 | 実行命令遂行状態のモニタ方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56171498A JPS5875256A (ja) | 1981-10-28 | 1981-10-28 | 実行命令遂行状態のモニタ方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5875256A true JPS5875256A (ja) | 1983-05-06 |
| JPS6148181B2 JPS6148181B2 (enExample) | 1986-10-23 |
Family
ID=15924208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56171498A Granted JPS5875256A (ja) | 1981-10-28 | 1981-10-28 | 実行命令遂行状態のモニタ方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5875256A (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5969853A (ja) * | 1982-10-15 | 1984-04-20 | Fujitsu Ltd | 履歴情報記録圧縮方式 |
| JPH0233631A (ja) * | 1988-07-22 | 1990-02-02 | Fujitsu Ltd | 先行制御トレース方式 |
-
1981
- 1981-10-28 JP JP56171498A patent/JPS5875256A/ja active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5969853A (ja) * | 1982-10-15 | 1984-04-20 | Fujitsu Ltd | 履歴情報記録圧縮方式 |
| JPH0233631A (ja) * | 1988-07-22 | 1990-02-02 | Fujitsu Ltd | 先行制御トレース方式 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6148181B2 (enExample) | 1986-10-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5479616A (en) | Exception handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exception | |
| US7689867B2 (en) | Multiprocessor breakpoint | |
| JP2001519956A (ja) | アドレスされた構成部分の思索の失敗を検出するメモリ・コントローラ | |
| JP2001519953A (ja) | マイクロプロセッサの改良 | |
| JP3773769B2 (ja) | 命令のインオーダ処理を効率的に実行するスーパースケーラ処理システム及び方法 | |
| JP3130446B2 (ja) | プログラム変換装置及びプロセッサ | |
| US4747045A (en) | Information processing apparatus having an instruction prefetch circuit | |
| US5469552A (en) | Pipelined data processor having combined operand fetch and execution stage to reduce number of pipeline stages and penalty associated with branch instructions | |
| JP4703718B2 (ja) | 選択的サブルーチンリターン構造 | |
| JPH0728670A (ja) | 情報処理装置 | |
| JP2817786B2 (ja) | シミュレーション装置及びシミュレーション方法 | |
| KR100263262B1 (ko) | 마이크로프로세서 | |
| US6651164B1 (en) | System and method for detecting an erroneous data hazard between instructions of an instruction group and resulting from a compiler grouping error | |
| JPS5875256A (ja) | 実行命令遂行状態のモニタ方式 | |
| JP2002163126A (ja) | デバッグ用cpuに内蔵のイベント検出回路、イベント検出方法および外部周辺回路 | |
| EP0569987A1 (en) | Microprocessor incorporating cache memory enabling efficient debugging | |
| JP2536726B2 (ja) | マイクロプロセッサ | |
| JPH06103109A (ja) | データプロセッサ、及びこれを用いるデバッグ装置 | |
| US7240185B2 (en) | Computer system with two debug watch modes for controlling execution of guarded instructions upon breakpoint detection | |
| JP2532560B2 (ja) | 高機能な例外処理を行うデ―タ処理装置 | |
| EP0525672A2 (en) | Microprocessor with program tracing | |
| JPS6293733A (ja) | マイクロプログラム制御式デ−タ処理装置 | |
| JP2644104B2 (ja) | マイクロプロセッサ | |
| JP2701799B2 (ja) | マイクロコンピュータ | |
| JPS6358539A (ja) | マイクロプロセサ |