JPS587071B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device using selective epitaxial technology and a method for manufacturing the same.

Generally, means for epitaxially growing crystals of the same type or different types on a crystalline substrate are broadly classified into liquid phase method, gas phase method, and molecular beam method.

In the liquid phase method and the gas phase method under atmospheric pressure, the density of substances directly or indirectly involved in crystal growth is high on the crystal growth surface, and the mean freedom of the elements constituting the epitaxial crystal (hereinafter referred to as crystal constituent elements) is high. Due to the short steps, this is a growth method in which these elements are supplied onto the substrate from completely random directions.

On the other hand, in the molecular beam method and some gas phase methods (e.g. pyrolysis method) that grow crystals under reduced pressure, the supply source of the crystal constituent elements (
For example, the mean free path l of the molecules of the molecular beam or the pyrolyzed substance can be kept sufficiently longer than the distance L between the substrate surface (for example, the molecular beam source, the supply nozzle for the pyrolyzed substance) and the substrate surface (i.e., g》L).
), it is possible to define the direction in which the crystal constituent elements reach the crystal growth surface.

Figure 1 shows an example of molecular beam selective evitaxy that utilizes this feature.

This example is (A, Y, cho, App6 Phys Le
21 355, (1972)).

That is, Ga and As2 are deposited on the substrate 1 from the molecular beam source 2.
Al molecules are supplied from the molecular beam source 3.

Furthermore, by interposing a thin tungsten wire 4 in the path of the molecular beam, a portion 5 on the substrate 1 that is in the shadow of the tungsten wire 4 contains Ga and As.
Only Ae reaches the portion 6 on the substrate 1.

The epitaxial layer 7 grown in this way contains G
It is known that different growth layers of composition X of a I X A (l X A s) can be made.

However, with the method shown in FIG. 1, although it is possible to form the different regions of the set lx linearly in the direction perpendicular to the plane of the drawing, it is difficult to form the above-mentioned regions curved into an arbitrary shape.

The present invention uses an epitaxial growth method that does not require a special shield such as a tungsten wire as described above and allows selective epitaxy even for curved shapes, and a semiconductor device having a new self-aligned arrangement and a method for manufacturing the same. It provides:

Here, a conventional self-aligned semiconductor will be briefly explained in order to clarify the difference from the present invention.

FIG. 2 shows a conventionally known field effect transistor having a Pn junction gate and having a self-aligned arrangement.

First, an n-type GaAs substrate 10 is formed on a semi-insulating GaAs substrate 10.
As active layer 11, P-type Ga1-XAlXAs layer 12,
The P-type GaAs layer 13 is continuously grown evixically.

Thereafter, the P-type GaAs layer 13 is selectively etched leaving the gate portion, and then the P-type Ga1
Side-etch the gate to form a so-called T-shaped gate, and
The GaAs active layer 11 is exposed.

Next, when the electrode layer 14 is deposited, the source, drain, and gate regions are separated from each other.

14a, 14b, and 14c are a source, a drain, a gate, and a drain electrode, respectively.

The problem with this device is that it is limited to a relatively low electron concentration (1015<n<1017) due to the design of the semiconductor device itself.
And thin o. In order to deposit electrode metal directly on the active layer 11 of iμ to 1μ, the source 14a and drain electrode 1
It is difficult to keep the contact resistance of 4c low, and furthermore, it is difficult to form an ohmic electrode without penetrating the active layer 11, which is a thin channel region on the substrate.

FIG. 3 shows the conventional structure of a Schottky barrier field effect transistor.

An active layer 16 is epitaxially grown on a semi-insulating GaAs substrate 15 and mesa-etched as shown in the figure to form titanium (Ti) 17, molybdenum (Mo) 18,
After continuous vapor deposition of gold (Au) 19, a gate vacuum made of gold (Au) 19 is created by photo processing, and using this as a mask, molybdenum (Mo) and titanium (Ti) are side-etched to determine the effective gate length.

Then, ohmic contact electrode metal 20 is vapor deposited and alloyed to form source, gate, and drain electrodes 20a, 20b, 20c.
A semiconductor device is constructed by forming a semiconductor device.

In this device as well, as in the above description, it is difficult to reduce the resistance of the source and drain electrode contacts.

FIG. 4 also shows another conventional structure example of a similar field effect transistor.

That is, an n-type active layer 22 and an n+ layer 23, which will become a channel, are continuously grown epitaxially on a semi-insulating substrate 21.

Next, after forming the source and drain electrodes 24a and 24b into a predetermined shape, an undercut mask for the gate portion is created by photo processing, and the layer 23 is shaped into the shape shown in the figure using an anisotropic etchant of bromine-metal. Reverse mesa etching is performed as shown in 25 to expose the n-type active layer 22.

Next, by depositing the electrode metal layer 26 on the gate portion by vapor deposition, a Schottky gate of a predetermined shape is formed.

In the configuration example of this device, the source and drain contacts are made using the n+ layer 23.
However, in the case of a minute gate, there is a problem in that it is difficult to reduce the resistance of the gate part itself because it is limited by the width and thickness of the metal forming the gate.

As explained above, the present invention provides a semiconductor device having a structure that eliminates the conventional problems and drawbacks such as difficulty in the manufacturing process, and a method for manufacturing the same.

First, to explain the outline of the present invention, a structure with a special geometrical shape is formed on a crystalline substrate, and the relationship between this structure and the incident direction of the crystal constituent elements allows crystals to be formed in a specific region on the crystalline substrate. Selective epitaxy is performed by allowing the constituent elements to fly in and not to other parts, or by changing the flying probability.

As a means of epitaxy, the mean free path e of the crystal constituent elements is smaller than the distance L between the supply source of the crystal constituent elements and the substrate surface.
It is only necessary to set the conditions to increase the .

Below, as a specific example of the present invention, the structure and manufacturing method of a field effect transistor using GaAs will be explained. Each major process unit will be explained in detail with drawings.

Figure 5.6.7 shows a method of making a junction field effect transistor (FET) according to the present invention;
is a schematic plan view of the state in which the gate part of the FET is formed;
．． c, d are BB' of a. It is a sectional view taken along lines CC' and D-o'.

A. Multilayer eviction process As is clear from FIG. 5, a 5 μm thick semi-insulating buffer layer 3 l is formed on a semi-insulating substrate 30 having a (001) plane.
(n = 5 x 1016cm3, thickness 0.4μm)
n-type GaAs active layer 32, (P>5×1017 Cm−
3, thickness 3 μm) of P+ type Ga0.7 Al. 3 A
s layer 33, (P>5X10-l7cx",
P+ type GaAs layers 34 each having a thickness of 2 μm are sequentially grown epitaxially.

B Etching process After that, an etching mask was formed by a photo process using the S L3 N4 film 35 deposited on the multilayer film grown in the multilayer epitaxial process so that the direction of the gate width was parallel to the <110> direction. .

Next, an anisotropic etching solution (S, Iida and K.
Ito: J. EJ? electrochem
Sot. 118, 768 (1971)) until the aforementioned semi-insulating layer 31 is reached, and then the Si3N4 mask 35 is removed.

FIG. 5a shows the shape of the P+ type GaAs layer 34 thus produced, and shows the relationship between the crystal axis directions of the gate pad portion 40 made of this layer 34 and the gate electrode portion 50 made of the same layer 34.

The broken line in FIG. 5a indicates the lower part of the broken lines in b, c, and d.

To further explain this process, the gate electrode portion 5 having an end surface along the <110> direction is formed by the anisotropic etching.
0 is formed in a mesa shape with an inclination of 45 degrees, and the gate pad portion 40 having boundaries in the <1 0 0>, <1 0 0>, and <0 1 0> directions has an inverted mesa and a vertical end face, respectively. It is composed of

Furthermore, the epitaxial layer 33 is etched by H3P04-based composition selective etching that selectively corrodes only Ga1-XAlXAs, using the P-type QaAs layer 34 as a mask to remove a part of the epitaxial layer 33 (the part outside and on the side of the dotted line 33). ) side etched.

Through this step, a P<0> type GaAs layer 33 having a width narrower than the P<0> type GaAs layer 34, that is, a gate region is formed, and a part of the n type GaAs active layer 32 is exposed.

This active layer 32 is C-C', D when viewed from the direction perpendicular to the main surface.
-D' line part has a structure in which the end portion is exposed only at the BB' part due to the shadow of the canopy of the P WGaAs layer 34.

On the other hand, the surface precision obtained by anisotropic etching is extremely high and exceeds the precision of the etching mask end face formed by photoprocessing.

Therefore, in this process of determining the most important gate length of a field effect transistor, first, anisotropic etching is performed to remove a mask made of the P+ type GaA6As layer 34 and a mask made of the P+ type GaA6As layer 34.
Il? After accurately forming the end face of the As 3 3, selective side etching of a portion 33' of the P+ type GaAeAs layer 33 is performed to form a uniform and highly accurate P layer over the entire gate width.
A ten-shaped GaA13As remaining portion 33 (ie, a gate portion) is formed.

C. Selective Ebiaxial Step Next, a layered GaAs layer 36 is grown by molecular beam method on the crystal plane (hereinafter referred to as substrate) that has gone through the above steps.

That is, as shown in FIG. 6a showing the arrangement of the molecular beam source and the substrate, a substrate 61 is placed on a substrate holder 60 that can be heated and temperature controlled.
The back sides of the metal are brought into contact with each other through the liquid metal.

62.63 and 64.65 are molecular beam sources whose temperatures can be controlled independently, and each has a Knudsen cell made of high-purity graphite, each containing Ga, As, Ge, and As.
Above. As and GaAs sources are primarily used to supply arsenic molecules, and Ge sources are the source of Ge, which is used as an n-type dopant.

With this configuration, the entire device is 5 x 1 0-10m7ILH
After evacuation to an ultra-high vacuum of 9 or higher, As radiation source 63.65
While heating and supplying As4 molecules onto the substrate, the substrate was heated and held at 610°C for 10 minutes to thermally etch the surface.Then, the substrate temperature was held at 550°C, and the substrate was heated to a predetermined temperature beforehand. The shutters of the molecular beam sources 63, 64, and 65 are opened to perform epitaxial growth, and 1×1018C1r
L-3Ge-doped n0-type GaAs is grown to a thickness of 1 μm.

The total pressure inside the manor during growth is approximately 5 x IQ ”myHg
Met.

At this pressure, as described above, the mean free path e of the molecular beam is sufficiently larger than the distance between the substrate and the radiation source (L=8cIrL), and the molecular beam reaches the substrate without being scattered along its path.

On the other hand, since the degree of unevenness formed on the substrate (see FIG. 5) is at most 10 μm, which is a minute amount of about 10 −4 compared to L, each molecular beam is incident almost like a parallel ray.

That is, as shown in FIG. 6B, in response to molecular beam irradiation from a radiation source 62 having an aperture diameter of 2R=67n11L, an n-GaAs. The width 2w of the umbra to the surface of s 3 2 and the distance U from the center to the edge of the penumbra are given by the following from the relationship of similarity.

d=3X1 0-4CrrL. d/ as L=8crn
If L is ignored relative to 1, the influence of the second term on the right side of the above equation on the width of the shadow is about 0.2μ, and this value is about the same as the surface diffusion length of molecules on the heated substrate surface. becomes.

3 due to the inclination angle θ of the molecular beam incident direction from the normal to the main surface of the substrate
The effect of the molecular beam wrapping around the lower part of the canopy in No. 4 is larger than this, and is on the order of d·tanθ.

At θ-25° this effect reaches about 1 μm. In order to utilize this wraparound effect, in this embodiment, as shown in FIG.
The ray sources each have an azimuth angle of 1 from the θ-25°〈1〒0〉 axis.
They were installed at 80°, 90°, and 0° positions.

In this way, it is possible to prevent Ga and Ge from going around to the bottom of the canopy, and to selectively introduce As only to the bottom of the canopy, thereby preventing a high resistance in the epitaxial layer of the exposed thin active layer.

From the above, it is clear that crystals do not grow in the shadow part of the canopy, and the width of the non-growing part is almost equal to the width of the canopy.

FIG. 7 shows the structure after epitaxial growth has been performed on the substrate shown in FIG.

In other words, through this process, the bottom of Hisashi (P-GaAlA
The n+ type GaAs layer 36 is not grown on the removed portion of s33', and forms part of the semi-insulating layer 31, the n+ type GaAs active layer 32, the gate electrode portion, and the gate pad portion. Separated n+ type GaAs layers 36a, 36b, and 36c can be formed on the P+ type GaAs layer 34, respectively.

Here, 36a is a gate electrode part, 36b is a source electrode part,
36c is a drain electrode portion.

That is, FIG. 7a is a schematic plan view after forming each gate electrode part, and FIG. 7b, c, and d are B-B', C of FIG. 7a.
-C', D-D' line sectional view.

As is clear from the above-mentioned figures 7a, b+c, and d, the n+ type GaAs selective epitaxial layer 36 is formed into an active layer by using the inclined end face structure by anisotropic etching and the composition selective etching and selective epitaxy of GaAIJAs mixed crystal. Grows in a self-aligned manner on the n-type GaAs 32 while maintaining electrical contact, forming the source and drain regions, as well as the active layer n-type GaAs 32 under the gate pad and the n+-type GaAs layers 36b and 3 for the source and drain electrodes.
It is insulated and separated from 6c.

Furthermore, the P+ type GaAs layer 34 on the top of the gate and the N+ type GaAs layer 36a epitaxially formed thereon are mutually highly doped layers and are forward biased during operation, so there is no problem in applying the gate voltage.

D Electrode Formation Step After completing steps B, B, and C, Au:
If electrode metals such as Ge/Ni are vapor-deposited, the electrode metals (not shown) will also become 36a, 36b, and 36c, respectively, as in step C.
self-aligned on top.

Then, by alloying these electrodes, a field effect transistor is completed.

That is, according to this electrode process, low resistivity n+Ga
Since the electrode metal is brought into contact with the As layer, the contact resistance is extremely small, and the relatively thick n+GaAs layer 36a
, 361), 36c can be alloyed with the electrode metal, which simplifies the manufacturing process.

In order to make it easier to understand the content of the present invention, Ga
Although an example of manufacturing a field effect transistor using As/GaAlAs has been described, the present invention is not limited to the scope of the above example. If this is true of the basic idea, it goes without saying that similar effects can be expected for each process and material as described below.

A Multilayer epitaxial process; This process uses liquid phase method, gas phase method,
It can be carried out continuously or by a combination of conventional means such as molecular beam method.

B Etching process; b-1 H2SO4:H20 as anisotropic etching
2: H20-based solution was used, but other general anisotropic etching solutions (bromine/methanol-based, citric acid: H2
0:H20 system, NH40H:H20:H20 system, H3P
O4; H20: H20 series, etc.) can also be used depending on the purpose.

Ordinary mesa etching solutions can also be used.

b-2 In this example, the active layer was completely removed except for the gate portion, but a modification may be considered in which a portion of the active layer remains.

b-3 In the example, composition selective etching of GaAgAs/GaAs was used, but even if the composition is not a mixed crystal, a combination of a chemical solution and an epitaxial layer with different etching rates depending on the impurity concentration and type of impurity can also be used to create a multilayer epitaxial film. Structures similar to the inventive structure can be formed.

C Selective epitaxial process; C-1 Strict conditions that can define the direction of the desired epitaxial film constituent elements onto the substrate e >> L
However, the intended purpose can be achieved even if l≧L, depending on the arrangement of the structure on the substrate surface and the structure shape.

Although the molecular beam method was used in the main step of Example c-2, other chemical transport methods and thermal decomposition methods were used under reduced pressure (pressure < 10-3 im).
Hg), the condition of l≧L is satisfied, and the flying direction of the desired epitaxial crystal constituent elements can be determined.

D Material: GaAs is shown in the example, but other ■
・■ Group semiconductors and their mixed crystals, ■ and ■ group semiconductors, Ge and Si
The idea of the present invention can be applied as is to group III semiconductors such as the following.

(In particular, for Si grown on sapphire, it is assumed that a device with a similar structure can be created by combining a chemical liquid treatment whose etching rate is dependent on impurity concentration and a pyrolytic epitaxy method under reduced pressure. Ru.

) As detailed above, the field effect transistor manufactured by applying the method of the present invention has the following features.

(1) Source, drain, and gate are arranged in self-alignment.

(2) Self-alignment is possible for the entire device including the gate pad.

(3) The contact resistance of the source and drain electrodes can be reduced due to the presence of the low resistivity crystal layer, ? 4) Since a T-shaped gate structure can be created, gate resistance is low even in devices with a minute gate length.

(5) A gate manufacturing process that combines anisotropic etching and compositional selective etching enables the manufacture of uniform and highly accurate gates.
Moreover, no increase in capacity occurs.

(6) With the above, higher frequency and lower noise can be expected.

(7) Manufactured using an extremely simple process that does not require mask alignment.

In this manner, the present invention can easily form a semiconductor device having a self-aligned arrangement.

[Brief explanation of the drawings] Figure 1 is an illustration of the conventional molecular beam epitaxial method in which the direction of incidence of crystal constituent elements on the substrate is specified Figure 2 2.3.4
The figure shows the conventional structure of a self-aligned field effect transistor.
FIG. 5 shows the manufacturing process of a junction field effect transistor according to an embodiment of the present invention in which a multilayer epitaxial film is formed on the main crystal surface by anisotropic etching and composition selective etching, and a is a schematic plan view thereof; b, c, d are B-B' of the same a
, C-C', D-D cross section; FIG. 6a is an explanatory diagram of the molecular beam epitaxial method used in the embodiment of the present invention to specify the direction of incidence of crystal constituent elements onto the substrate; The same b is a
Figure 7 shows the structure of the main part of a field effect transistor grown by applying the method shown in Figure 6 to Figure 5, characterizing the incident direction of the crystal constituent elements, and epitaxy using a Hisashi. The layout is shown in the same figure, where a is a schematic plan view thereof, and b, c, and d are B-B', C-C' of the same a.
, is a sectional view taken along line DD'. 30... Semi-insulating substrate, 33... P-type GaA11As layer (gate), 34. ．． ．． -P+ type G
aAs layer, 36a, 36b, 36c-n
+ type Ga As layer, 62-65... Molecular beam source.

Claims (1)

[Scope of Claims] 1. A step of forming two or more evictaxial crystal layers with different properties on at least one principal surface of a crystalline substrate, forming a resist pattern on the uppermost evitaxial crystal layer, and forming a resist pattern on the uppermost epitaxial crystal layer, A step of selectively etching the epitaxial crystal growth layer of the substrate by an etching means, and then selectively etching a part of the lower epitaxial crystal layer using the upper epitaxial crystal layer as a mask to form a specific pattern on the crystalline substrate. a step of forming a structure;
a step of forming a new epitaxygyl crystal layer on a crystal plane including the structure, in the step of forming the new epitaxial crystal layer, a supply source for supplying crystal constituent elements to be grown and the substrate; Manufacturing a semiconductor device, characterized in that crystal growth is performed by specifying the flying direction of the molecules containing the crystal constituent elements under conditions that increase the mean free path of the gas molecules containing the crystal constituent elements compared to the distance between the crystal constituent elements. Method. 2. A method for manufacturing a semiconductor device according to claim 1, characterized in that a molecular beam epitaxial method is used as a means for crystal growth.