JPS6050957A - Hetero junction bipolar semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the base resistance and the emitter junction area of a semiconductor device by laminating a collector, a base, and an emitter of the prescribed energy band width Eg on a semiconductor substrate, cutting-out to the base layer with electrodes as masks, filling the cut-out with the same conductive type layer as the base, and attaching a base electrode to the surface. CONSTITUTION:An N<+> type buffer 12, an N type collector 13, a P<+> type base 14, an N type Al0.3Ga0.7As emitter 15, and an N<+> type cap layer 16 are laminated on an N<+> type GaAs substrate 1 by a molecule beam epitaxial method, a Ge film 17 and a W5Si3 film 18 are laminated, an emitter electrode 20 is formed by a resist mask 19, and etched to form a cutout 21, thereby exposing the base 14. A P<+> type Al0.3Ga0.7As film 22 is selectively grown at the cutout, an Au film 23, a Zn film 24 and an Au film 23' are superposed, an AuGe film 26 and an Au film 27 are superposed on the back surface of the substrate, alloyed to form collector electrodes 28, the metal layer of the surface is patterned, alloyed to form a base electrode 25 to complete this. The layer 15 needs Eg wider than the layer 14. According to this construction, ultrafine pattern can be formed accurately, thereby reducing the semiconductor device with good reproducibility.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to an improvement in a heterojunction bipolar semiconductor device having an emitter or an emitter and a collector having an energy hunting gap wider than the energy hunting gap in the Haas.

Prior Art and Problems In general, the emitter common current amplification factor β in a bipolar transistor has the following relationship: β-α/(1-α) α: Haas common current amplification factor; α has the following relationship: α; γ・7 γ: Injection efficiency 7 = @Transmission efficiency.

Therefore, the closer α is to 1, the larger β becomes, and in order to make α closer to 1, T should be made closer to 1.

The above-mentioned heterojunction bipolar semiconductor device has a characteristic in which T is extremely close to 1, so that it is possible to obtain a large grounded emitter amplification factor β, and therefore its development has been active in recent years.

By the way, currently, compound semiconductors, especially GaAs, are used as materials for manufacturing heterojunction bipolar semiconductor devices.
/AAGaAs system is used, however, there are many difficulties in simply growing crystals of this material, and even more so, it is nearly impossible to perform complex processing such as silicon-based semiconductor devices.

Therefore, the realized heterojunction bipolar semiconductor device has an extremely simple structure.

FIG. 1 is a cross-sectional side view of essential parts of a conventional heterojunction bipolar transistor.

In the figure, 1 is an n+ type GaAs semiconductor substrate, 2 is an n- type GaAs semiconductor substrate with a thickness of about 3000 to 3 [μm].
Collector layer, 3 is a p + type GaAs base layer with a thickness of about 500 [μm] to 1 (μm), 4 is an n-type A with a thickness of about 2000 [μm] to 2 (μm) 7!0.3G a
O,7A S emitter layer, 5 is n+ type GaAs cap layer, 6 is gold/germanium/gold (Au/Ge/A
7 is Au/71, u.
Base electrode made of zinc (Zn), 8 is Au・G e
/ A u emitter electrode, 11 is the base electrode 7
and the alignment margin between the emitter layer 4 and the emitter layer 4, and β2 indicate the alignment margin between the emitter layer 4 and the emitter electrode 8, which is 1.13, and the minimum required length of the emitter layer 4, respectively. Note that the minimum required length means, for example, the minimum necessary side length if the emitter layer 4 is square, and the minimum necessary diameter if it is circular.

Now, in the conventional example shown in the figure, if it were to be manufactured using current technology, 7!1 would require 2 [μm], and if it is less than that, there will be a problem in terms of manufacturing yield. Also, β2
For the same reason, 2 [μm] is required. Furthermore, although it is somewhat difficult, assuming that the width or diameter of the emitter electrode 8 is within 1 [μm], the width or diameter of the emitter electrode 8 is 5 [μm].
〕is necessary.

As can be seen from the above description, in this type of transistor, the area of the emitter layer 4 in plan view is quite large, and in addition, since the distance between the emitter layer 4 and the base electrode 7 is large, the base resistance increases. has no choice but to be high.

In order to reduce this base resistance, it is sufficient to increase the impurity concentration of the base layer 3, but for example, even if ion implantation is applied to compensate, at most 5×1o18 (c+n-3
), and approximately βcx=pJ,
/pJBNE: Emitter layer impurity concentration NB: Base layer impurity concentration Therefore, if the impurity concentration of the base layer is set too high, the common emitter current amplification factor β will decrease.

Furthermore, as described above, since the emitter layer 4 has a large area when viewed in plan, the pn generated between it and the base layer 3
The area of the junction is also large, and therefore the junction capacitance in that part is also quite large, and as seen in the above explanation, the switching speed is inevitably reduced due to the large base resistance. I'm in a state where I can't get it.

Moreover, as described above, the area of the emitter layer 4 is large, and the area between the base electrode 7 and the emitter layer 4 must also be made large due to alignment margin, so the overall size becomes large. Moreover, since high-precision processes are required to form each part, reproducibility is poor.

Purpose of the Invention The present invention provides a structure that can reduce the base resistance and the emitter junction area, resulting in a reduction in the overall area, and also allows a highly accurate pattern to be obtained with good reproducibility. A heterojunction bipolar semiconductor device is provided.

Structure of the Invention The heterojunction bipolar semiconductor device of the present invention comprises at least a collector layer and a base layer grown on a semiconductor substrate, an emitter layer having an energy hand gap wider than the base layer, and the laminated layer. A cutout portion is formed by removing the layer from the surface using an electrode selectively formed on the top layer of the layer as a mask until at least the base layer is exposed, and the cutout portion is filled and has the same conductivity as the base layer. It has a structure comprising a semiconductor crystal portion which is a mold, and a base electrode formed on the surface of the semiconductor crystal portion.

With such a structure, the patterning of the emitter vine layer is performed in a self-alignment manner, and
The semiconductor crystal portion can be grown by selective epitaxial growth.

Embodiment of the Invention FIGS. 2 to 6 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining the case of manufacturing an embodiment of the present invention. I will explain while referring to it.

See Figure 2 ■ MBE (molecular beam epi)
Taxy> method is applied to deposit I on the n+ type GaAs substrate 11.
n with an impurity concentration of X 10 ” (cm−3)
The +-type GaAs buffer layer 12 is made of n-type Ga with a thickness of about 2000 [people] and an impurity concentration of LXIO'' (button -3).
The As collector layer 13 has a thickness of about 4000 [people], I
A p+ type Heath Jit14 with an impurity concentration of 10" (cm-3)) has a
n-type A with an impurity concentration of x 10” (cm-3)
11 o, 3G a 0.7A S emitter Jttj
15 with a thickness of about 3000 [people], two layers of 10 weight B (cm
-3) n+ type A j2o, 3G with impurity concentration
a 0.7A Scan 1 layer 16 is grown in order to a thickness of about 1000 (people).

Refer to FIG. 3 ■ Applying the vapor deposition method, a germanium (Ge) layer 17 is formed to a thickness of about 200 μm.

■ Using RF sputtering, tungsten silicide (Ws Si 3) JWI 8 was deposited to a thickness of 5000 mm.
form to the extent of a person.

■ Applying photolithography technology, pattern the W 6 Si 3 layer 18 and GeN 11 using the photoresist film 19 as a mask, and pattern YAG from the back side.
Alloying is performed by laser irradiation to form an ohmic contact emitter electrode 20.

Refer to Figure 4 ■ Using the emitter electrode 20 as a mask, the cap layer 16 is
, the emitter 15, the base layer 14, and the collector IW 13 are etched to form a notch 21. In this case, etching must be performed until at least the base layer 14 is exposed.

See Figure 5 ■ Trimethyl gallium, trimethyl aluminum,
MO using a mixed gas consisting of arsine and diethylzinc
CVD (metal organic chemical
al vapor dep.

5ition) method and using the emitter electrode 20 as a mask, p1 type A 7!0.3 Ga o, 7 A s
Semiconductor crystal portion 22 is selectively grown. Since the growth temperature at this time is about 700 ('C), the emitter electrode 20 is not thermally adversely affected.

Refer to Fig. 6 ■ By applying the vapor deposition method, the Au layer 23 is made to a thickness of about 100 [people], the Zn layer 24 is made to a thickness of about 100 [people], and the Au layer 23 is made to a thickness of about 100 [people].
' is formed to a thickness of about 3000 (person).

■ Au-Ge layer 26 on the back side of the n+ type GaAs substrate 11
was formed to a thickness of about 200 mm, and then an Au layer of 27 mm was formed.
The collector electrode 28 is formed by forming a film with a thickness of about 2,000 mm and subjecting it to a heat treatment for 1 minute at a temperature of 450 degrees Celsius for alloying.

■ By applying photolithography technology, the Au layer 23'
, Zn 124, and Au layer 23 are patterned, and a heat treatment is performed at a temperature of 300 ('C) for 1 minute to form a heath electrode 25 for alloying.

The heterojunction bipolar semiconductor device completed as described above has emitter dimensions of 2 [μm]×5 Cμm).
and hpE=1500, IT”30 (GHz)
was gotten.

In the present invention, the energy hand gap of the emitter layer 15 needs to be wider than that of the base layer 14, but the energy hunt gap of the collector layer 13 may be either.

If the collector layer 13 is also made of a semiconductor with a wide energy hand gap, the collector layer N
It is also possible to exchange the positions of the emitter layer 13 and the emitter layer 15, in which case each layer will be etched using the collector electrode as a mask. As described above, at least the base layer 14 is exposed.

Further, even if the semiconductor crystal portion 22 filling the notch portion 21 has an energy band gap wider than that of the base layer 14 as seen in the above embodiment, it may have the same energy band gap. Also good.

Furthermore, the GaAs substrate may be insulating, but in that case, the collector electrode (or emitter electrode)
must be extracted from the surface of the semiconductor device. To do so, the buffer layer is selectively exposed by etching from the surface and the electrodes are led therefrom.

Effects of the Invention In the heterojunction bipolar semiconductor device of the present invention,
At least a collector layer and a base layer grown on a semiconductor substrate and an emitter layer having an energy hand gap wider than the energy hand gap of the base layer, masking an electrode selectively formed on the top layer of the stacked layers. A cutout portion formed by removing the layer from the surface until at least the base layer is exposed, a semiconductor crystal portion filling the cutout portion and having the same conductivity type as the base layer, and a semiconductor crystal portion formed on the surface of the semiconductor crystal portion. Since the structure is equipped with a base electrode, the emitter layer is patterned using a self-alignment method using the electrode formed on the top layer of each layer grown on the semiconductor substrate as a mask. Therefore, the emitter-base junction area in plan view is extremely small, and the semiconductor crystal portion with which the base electrode is in contact is formed by selective epitaxial growth. Therefore, the impurity concentration can be made higher than when relying on ion implantation, for example, and the base resistance can be reduced as a whole.

Incidentally, since the effective impurity concentration in the base layer is appropriately selected and the base layer can be formed thin, there is no adverse effect on the current amplification factor. Further, as described above, since the emitter-base junction area is small, the junction capacitance can be reduced, and this together with the small base resistance improves the switching speed.

Even more! Because of the structure, it is possible to adopt a self-alignment method for patterning, so it is possible to form fine patterns with high precision without any difficulty, and it is possible to make heterojunction bipolar semiconductor devices compact with good reproducibility. It is effective for

[Brief explanation of drawings]

FIG. 1 is a cutaway side view of a main part of a conventional example, and FIGS. 2 to 6 are cutaway side views of a main part of a semiconductor device at important process points for explaining the manufacturing of an embodiment of the present invention. It is. In the figure, 11 is an n+ type GaAs substrate, 12 is an n+ type GaAs buffer layer, 13 is an n type GaAs collector layer,
14 is a p" type base layer, 15 is an n type A 1i o, 3G
a 0.7A S emitter layer, 16 is n+ type A A
0.3G a O, 7A S key I'll/p layer, 17
is a Ge layer, 18 is a Wc, Si three layer, 19 is a photoresist film, 20 is an emitter electrode, 21 is a notch part, 22 is a p+ type A j2o, 3Gao, 7A S semiconductor crystal part, 23 and 23' is an Au layer, 24 is a Zn layer, 2
5 is a base electrode, and 26 is an Au layer. Patent applicant Fujitsu Ltd. Representative Patent Attorney Shoji Aitani Representative Patent Attorney Hiroshi Watanabe - Figure 1 Figure 3 q Figure 4

Claims (1)

[Claims] At least a collector layer and a base layer grown on a semiconductor substrate, an emitter layer having an energy band gear wider than the energy band gear of the base layer, and an electrode selectively formed on the top layer of the stacked layers as a mask. a cutout portion formed by removing the layer from the surface until at least the base layer is exposed; a semiconductor crystal portion that fills the cutout portion and has the same 28-electrode type as the base layer; and a semiconductor crystal portion formed on the surface of the semiconductor crystal portion. 1. A heterojunction bipolar semiconductor device, characterized in that it comprises a base electrode with a base electrode.