JPS5870696A - Controller to be monitored - Google Patents
Controller to be monitoredInfo
- Publication number
- JPS5870696A JPS5870696A JP16929481A JP16929481A JPS5870696A JP S5870696 A JPS5870696 A JP S5870696A JP 16929481 A JP16929481 A JP 16929481A JP 16929481 A JP16929481 A JP 16929481A JP S5870696 A JPS5870696 A JP S5870696A
- Authority
- JP
- Japan
- Prior art keywords
- address
- input
- output
- crab
- monitored
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q9/00—Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Selective Calling Equipment (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は遠隔監視制御システムの被監視制御装置の母線
に接続されたN個の入出カニニット都合々にM個の入出
力ユニラミ持ち、これが2進数単位の連続したアドレス
を有し、1番目のアドレス金他目的のアドレスとして使
用し、監視制御装置からは該N個の入出カニニット部の
M個の入出カニニットの2番目のアドレスから連続した
アドレスで指定する場合、1番目のアドレスの入出カニ
ニットも使用可能な被監視制御装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention has N input/output units connected to the bus line of a monitored and controlled device of a remote monitoring and control system, each having M input/output units, which can read consecutive addresses in binary units. If the first address is used as an address for other purposes, and the supervisory control device specifies it as a consecutive address from the second address of the M input/output crab units of the N input/output crab units, the first address is used as an address for other purposes. This invention relates to a monitored control device that can also be used to enter and exit addresses.
第1図に従来例の被監視制御装置の要部の回路のブロッ
ク図を示す。FIG. 1 shows a block diagram of the main circuitry of a conventional monitored and controlled device.
図中1〜Nは入出カニニット部、1−0〜1−(M−i
)、2−0〜2−(M−1)t N−0〜N−(M−1
)は入出カニニット、10はモデム、11は直並列変換
回路(以後8/P変換回路と略称する)、12は並直列
変換回路(以後P/Sグこ換回路と略称する)、13は
母1iit−示す0下衣に例として入出カニニットの6
桁バイナリ−ビットで我社したアドレスを示す。In the figure, 1 to N are input and output crab knit parts, 1-0 to 1-(M-i
), 2-0~2-(M-1)t N-0~N-(M-1
) is the input/output crab unit, 10 is the modem, 11 is the serial/parallel converter circuit (hereinafter abbreviated as 8/P converter circuit), 12 is the parallel/serial converter circuit (hereinafter abbreviated as P/S converter circuit), and 13 is the motherboard. 1iit-shows 0 lower garments as an example of 6 in and out crab knits
Digit binary - indicates our address in bits.
入出カニニット部1〜Nは量産化のために各々にM個Q
入出力X = 、、tトt−!1!装するG又とOアド
レスとしては例えば上表の如く2進数率位で連続したア
ドレスを与える。Mが4の場合に例をとると上表の如く
入出力ユニツ)1−0に紘アドレスとしてoooooo
を2−0に拡000100を15−3には111011
t−与える0監視制御装置(図示していない)よシO
第1@に示す被監′aIII制御装置の入出カニニット
の制御はモデム10.8/P変換回路11、母@13J
−介して上!!Oアドレスにて入出カニエツト1−0〜
1−(犀−1−)、2−0〜2−(M−1>、 N−0
−N−(M−1)を指定し又応答は該入出カニニットか
ら自分のアドレスを付して母@113.P/S変換回路
12.モデムlOを介して行う0従ってこの時第1アド
レスooooo。Input and output crab knit parts 1 to N are each made of M pieces Q for mass production.
Input/output X = ,,ttt-! 1! As the G and O addresses to be installed, consecutive addresses in binary numbers are given, for example, as shown in the table above. For example, if M is 4, the input/output unit) 1-0 is set to oooooo as the Hiro address as shown in the table above.
Expand 000100 to 2-0 to 111011 to 15-3
t-gives 0 to the supervisory control device (not shown)
The control of the input/output unit of the supervised 'aIII control device shown in the first @ is the modem 10.8/P conversion circuit 11, mother @13J
-Via on! ! Incoming and outgoing Kanietsu 1-0 at O address
1-(Rhin-1-), 2-0 to 2-(M-1>, N-0
-N-(M-1), and the response is from the input/output crab unit to mother@113. with your own address. P/S conversion circuit 12. 0 through the modem IO, so at this time the first address oooooo.
を例えdJ!常を検出するデータのアドレスとして使用
すると入出カニニット1−0は使用出来なくなる。この
為1@入出カニニツトが無駄に彦ると共に例えば上表の
如く入出カニニットが60個ある場合60個使用したい
場合は被監視制御装置がもう一つ必要になるし、又(N
−1)XM個使用したい場合はN@O入出カニニット部
が必要となり高価になる欠点がある。For example, dJ! If this address is used as an address for data to detect normal times, input/output crab units 1-0 become unusable. For this reason, 1 @ input/output crab unit is wasted, and for example, if there are 60 input/output crab units as shown in the table above, if you want to use 60 units, another monitored control device is required, and (N
-1) If you want to use XM pieces, an N@O input/output crab knit part is required, which has the disadvantage of being expensive.
本発明の目的は上記の欠点をなくするために第X@目の
アドレスの入出カニニットも使用可能にすることによル
安価に構成出来る被監視制御装置の提供にある0
本発明は上記の目的を達成するためにアドレス11個ず
らせるアドレス変換回路t−具備し、入出力ユニツ)1
指定する場合監視制御装置からは2番目のアドレスから
指定しても、アドレス変換回路によルアドレスを1個ず
らして入出カニニットは1番目のアドレスのものから使
用出来るようにしたことt4IlFgLとする。The purpose of the present invention is to provide a monitored controlled device that can be constructed at low cost by making it possible to use the input/output function of the X@th address in order to eliminate the above-mentioned drawbacks. In order to achieve
When specifying, even if the supervisory control device specifies the second address, the address is shifted by one by the address conversion circuit so that the input/output crab unit can be used from the first address. t4IlFgL.
以下本発明の1実施例につき図に従りて説明する。第2
図拡本発明の実施例の被監視制御装置の要部の回路のブ
ロック図、第3wtJ線本発明Q案施例のアドレス変換
回路によるアドレス変換例を示すブロック図である。図
中第1図と同一機能のものは同一記号で示す@14,1
5,16uアドレス変換回路金示す。第2図の回路で第
1図と異なる点はアドレス変換回路14.15t−設け
た点であシ一般的な動作はIIL1図と同じである。又
アドレスとしては上記と同じく6桁バイナリピットで表
はした例で説明する0入出力二二、トの第1番目のアド
レス0000◇0を例えは異常を示すデータのアドレス
として使用したとすると、監視制御装置では入出カニニ
ットのアドレス指定としては第2番目のアドレスooo
ooiより連続番号で指定する。このアドレス脊骨を監
視制御装置より送信の場合はアドレス変換回路14にて
lアドレス減算して第3図に示す如く第111目のアド
レスooooooよシの連続番号に変換する0又入出カ
ニニツトよ)の応答の場合はアドレス変換回路15によ
シェアドレス加算してIH1番目のアドレスooooo
oよりの連続番号を持ったものを第3図に 。An embodiment of the present invention will be described below with reference to the drawings. Second
FIG. 3 is an enlarged block diagram of a circuit of a main part of a monitored control device according to an embodiment of the present invention, and a block diagram showing an example of address conversion by an address conversion circuit of a third wtJ line according to a Q embodiment of the present invention. Items with the same functions as those in Figure 1 are indicated by the same symbols @14,1
5,16u address conversion circuit gold is shown. The circuit of FIG. 2 differs from that of FIG. 1 in that address conversion circuits 14 and 15t are provided.The general operation is the same as that of FIG. As for the address, if we use the first address 0000◇0 of 0 input/output 22, which will be explained in the example shown above using 6-digit binary pits, as the address of the data indicating the abnormality, for example, In the supervisory control device, the second address ooo is used to specify the input/output crab unit address.
Specify sequential numbers from ooi. When this address spine is sent from the monitoring control device, the address conversion circuit 14 subtracts 1 address and converts the 111th address oooooo to a consecutive number as shown in Figure 3. In the case of a response, the address conversion circuit 15 adds the shared address and returns the IH 1st address oooooo.
Those with consecutive numbers starting from o are shown in Figure 3.
示す如く第2番目のアドレスoooooxよシの連続番
号に変換する@従って監視制御装置よシ第2番目のアド
レスoooooiで入出カニニットを指定するとm1番
目のアドレスoooooo t−持り九入出カニニット
1−0が指定され又入出カニニットl−〇よシの応答の
場合は監視制御装置へは第2番目のアドレス00000
1 ’を待った入出カニニットの応答の如く見える0こ
のことによシ入出力ユニ−ットは第1番目のアドレスo
ooo、oo t−持りた入出カニニットも使用出来る
。このため入出カニニットも無駄にならず又従来例で説
明した表の如く入出カニニットが60個ある場合60@
全部使用出来ω個使用したい場合被監視制御装置t−4
5一つ増設する必要はなくなる0又(N−1)XM個使
用したい場合(N−1)個O入出カニニット部でよい第
4図j15図は本発明の実施例OXアドレス減算する変
換回路及び1アドレス加算する変換回路の回路図である
。図中1〜Nは入出カニニット部、1−0〜1−(M−
1)* 2−0〜2−(M−t)tN−0〜N−CM
−1)は入出カニニット、10はモデム、txFis/
P変換回路、12はP/S変換回路、13は母線、14
,15.16はアドレス変換回路、21,221 24
.25はレジスタ、23紘1アドレス減算回路、26は
1アドレス加算回路、31〜3n、61〜6nFiノッ
ト回路、41〜43.81〜83はアンド回路、51〜
5n、71〜7nはEX−OR回路である。As shown, the second address ooooox is converted into a sequential number of shi. is specified, and if the input/output crab unit l-〇Yoshi response is sent, the second address 00000 is sent to the supervisory control device.
1 This looks like a response from the input/output crab unit that waited for 0. This causes the input/output unit to move to the first address o.
ooo, oo t-You can also use the in-out crab knit you have. Therefore, the incoming and outgoing crab knits are not wasted, and as shown in the table explained in the conventional example, when there are 60 incoming and outgoing crab knits, 60 @
If you can use all of them and want to use ω pieces, use the monitored control device t-4.
If you want to use 0 or (N-1)XM units, you can use (N-1) O input/output crab knit sections. FIG. 2 is a circuit diagram of a conversion circuit that adds one address. In the figure, 1 to N are input and output crab knit parts, 1-0 to 1-(M-
1)*2-0~2-(M-t)tN-0~N-CM
-1) is input/output crab unit, 10 is modem, txFis/
P conversion circuit, 12 is P/S conversion circuit, 13 is bus bar, 14
, 15.16 is the address conversion circuit, 21, 221 24
.. 25 is a register, 23 is a 1-address subtraction circuit, 26 is a 1-address addition circuit, 31-3n, 61-6nFi not circuit, 41-43.81-83 is an AND circuit, 51-
5n and 71 to 7n are EX-OR circuits.
′!If)lあ 72B P4図′! If)lah 72B P4 figure
Claims (1)
されたN個の入出カニニット都合々にM個の入出力ユニ
ツ)1−持ち、これが2進数単位の連続したアドレスを
有し、1番目のアドレスを他目的のアドレスとして使用
し、監視制御装置からは該N個の入出カニニット部のM
個の入出カニニットのアドレスとして2番目のアドレス
から連続したアドレスで指定する場合、該入出カニニッ
ト部が受信の場合はアドレ、スt−1個減算するアドレ
ス変換回路を応答の場合はアドレスを1個加算するアド
レス変換回路全使用するよう該毒婦の該監視制御装置側
に設けたことを特徴とする被監視制御装置。The busbar of the monitored and controlled device of the remote monitoring and control system 7 has N connected input/output units (conveniently M input/output units) 1, which have consecutive addresses in binary units, 1 The supervisory control device uses the Mth address of the N input/output crab units as an address for other purposes.
When specifying consecutive addresses starting from the second address as the address of the input/output crab unit, if the input/output crab unit is receiving, the address is specified, and if the input/output crab unit is responding, the address is 1. A monitored and controlled device characterized in that an address conversion circuit for addition is provided on the side of the monitoring and controlling device of the toxic woman so that all address conversion circuits are used.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16929481A JPS5870696A (en) | 1981-10-22 | 1981-10-22 | Controller to be monitored |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16929481A JPS5870696A (en) | 1981-10-22 | 1981-10-22 | Controller to be monitored |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5870696A true JPS5870696A (en) | 1983-04-27 |
JPS6355837B2 JPS6355837B2 (en) | 1988-11-04 |
Family
ID=15883846
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16929481A Granted JPS5870696A (en) | 1981-10-22 | 1981-10-22 | Controller to be monitored |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5870696A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4628478A (en) * | 1983-07-07 | 1986-12-09 | Motorola, Inc. | Remote data controller for a communication system |
-
1981
- 1981-10-22 JP JP16929481A patent/JPS5870696A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4628478A (en) * | 1983-07-07 | 1986-12-09 | Motorola, Inc. | Remote data controller for a communication system |
Also Published As
Publication number | Publication date |
---|---|
JPS6355837B2 (en) | 1988-11-04 |
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